ST18-AU1 STMICROELECTRONICS [STMicroelectronics], ST18-AU1 Datasheet - Page 27

• Manufacturer Part Number: ST18-AU1
• Description: SIX-CHANNEL DOLBY AC3/MPEG2 AUDIO DECODER
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

5.2 Input FIFO
Associated with input serial interface 0 (DIN0) is a 32 byte input FIFO. It is used for temporary
storage of incoming data during processing of packet headers or AC3/MPEG decoding. The
input FIFO provides the following:
5.2.1 Input FIFO registers
FIFOCR: Input FIFO control register
On reset, all bits are cleared. The FIFO is cleared and the formatter is set to the ‘empty’ state.
Bit
DREQ_EN
DMA_mod
FIFO_level
DREQ_SEL
DIN0_IEN
CLR_Form
-
15
-
14
-
13
-
transfer of data to the input buffer on a word basis
packet header processing when operating on PES
detection of FIFO overflow and FIFO filled to a predefined level
CLR_Fo
Function
DREQ enable
DMA mode
FIFO threshold level (MSB=7, LSB=3). Set FIFO filling level for IRQ/DREQ manage-
ment.
DREQ signal settings (if DREQ_EN = 1)
DIN0 interrupt enable
Set formatter empty (active only at write time of FIFOCR)
RESERVED, read as 0.
12
rm
0
1
0
1
0
1
0
1’
11
-
DREQ= 0
DREQ set according to FIFO threshold/full level
DMA request always enabled
DMA request enabled only when PDC not equal to 0 (PES
processing)
DREQ is asserted high when FIFO threshold is reached
DREQ is asserted high when FIFO is full (if DREQ_EN=1)
interrupt disabled
interrupt enabled (when FIFO_THS = 1)
DIN0_IE
10
N
9
-
DREQ_
SEL
8
7
6
FIFO_level
5
4
3
DMA_
mod
2
DREQ
ST18-AU1
_EN
1
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0
-