ST18-AU1 STMICROELECTRONICS [STMicroelectronics], ST18-AU1 Datasheet - Page 32

• Manufacturer Part Number: ST18-AU1
• Description: SIX-CHANNEL DOLBY AC3/MPEG2 AUDIO DECODER
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST18-AU1
PCMCR: Data in control register
All bits are cleared on reset.
32/87
Bit
PCMEN
WS
CLK_pol
WS_pol
Delayed
Justified
Mode
PCM_ord
15
-
14
-
13
-
Function
PCM output enable
Output word size
Clock pol
Word size pol
Delayed
Note: valid only for start justified mode, see bit 6.
If number of SCLKPCM cycles between WS transitions is > N (=Word size)
Mode
In 16-bit word-size,
Mute
_en
0
1
bit 1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
12
play mute PCM
11
disable
enable
bit 0
0
1
0
1
data and WS change on SCLKPCM falling edge
data and WS change on SCLKPCM rising edge
Left data word = WS low, Right data word = WS high
Left data word = WS high, Right data word = WS low
first bit of data occurs on transition of WS
first bit of data occurs with 1 SCLKPCM cycle delay relative to
transition of WS. (I
start justified: N bits read, starting from first bit:
just after WS transition if Delayed =’0’
with 1 clk cycle delay after WS transition if Delayed =’1’
end justified, end bit in last bit received:
just before WS transition if Delayed =’0’
just after WS transition if Delayed =’1’
2 channels
6 channels
MSB sent first
LSB sent first
10
_ord
word size
16 bit
18 bit
20 bit
24 bit
9
Mode
2
S compatible).
8
7
-
Justi-
fied
6
De-
layed
5
WS_p
ol
4
CLK_
pol
3
2
WS
1
MEN
PC-
0