ST18-AU1 STMICROELECTRONICS [STMicroelectronics], ST18-AU1 Datasheet - Page 26

• Manufacturer Part Number: ST18-AU1
• Description: SIX-CHANNEL DOLBY AC3/MPEG2 AUDIO DECODER
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST18-AU1
DIN0-1DIV: Data in division register
On reset, DIN0DIV value is set to 0.
DIN1DR: Data in output register
This 16-bit register contains the serial interface input data and is read by the D950.
26/87
Justified
Master
-
Bit
DINDIV
15
-
14
-
13
-
If number of Clk cycles between WS transitions is > n (= word size)
Master or slave operation
NOTE: this bit must be defined before the input interface enable (DINEN) bit is set.
RESERVED, read as 0.
Function
MCLK_DIN divide factor
f
RESERVED, read as 0.
CLKDIN
0
1
0
1
00000000’
00000001
.....
11111111
12
-
=
fMCLK_DIN
11
-
start justified: n bits read, starting from first bit:
just after WS transition if Delayed =’0’
with 1 clk cycle delay after WS transition if Delayed=’1’
end justified, end bit beein last bit received:
just before WS transition if Delayed =’0’
just after WS transition if Delayed =’1’
slave
master
10
-
/2(DIN0DIV) if DIN0DIV /= ‘00000
9
-
1
2
......
’510 ‘
8
-
7
6
5
4
DINDIV
3
2
1
0