ST18-AU1 STMICROELECTRONICS [STMicroelectronics], ST18-AU1 Datasheet - Page 52

• Manufacturer Part Number: ST18-AU1
• Description: SIX-CHANNEL DOLBY AC3/MPEG2 AUDIO DECODER
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST18-AU1
13.2 Clocks and timers registers
PSCTR register)
STC: system time clock registers
A Prescaler divides by 300 the master clock and generates the input clock at 90 KHz for STC.
The 90 KHz clock is synchronized to the D950 instruction clock.
STC is a 32-bit counter incremented at each 90 KHz clock pulse. It can be initialized to any
value and read by the D950. It is memory mapped as two registers, STCMTR and STCLTR.
STCMTR: 16-bit (MSB)
STCLTR: 16 bit (LSB)
Note:
No interrupts are associated with the STC.
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Bit
SCLKINT-
DIV
CLK_sel1
CLK_sel2
-
15
-
14
-
When initializing the STC, the STCLTR register must be written before the STCLMTR. The
effective loading of the STC occurs after STCMTR loading: When reading the STC, the
STCLTR register must be read first. At that time, the current value of the STC MSB is stored
in the STCMTR register, which can then be read.
13
-
Function
SCLKINTDIV prescaler divide factor
f
PCM output clock select:
PCM Output Clock select:
RESERVED, read as 0.
SCLKINT
input = EXTAL1 (27 MHz)
output = STC
00000000
00000001
...
11111111
0
1
0
1
12
-
=
11
fpll2
-
Hardware (MCLK_MODE pin)
Software (according to bit 9)
MCLK_PCM= output of prescaler: SCLK is system clock output
MCLK_PCM= SCLK: SCLK is system clock input
/2(SCLKINTDIV) if SCLKINTDIV /= 00000000
10
-
CLK_sel
1
2
...
510
9
2
CLK_sel
8
1
7
6
5
SCLKINTDIV
4
3
2
1
0