ST18-AU1 STMICROELECTRONICS [STMicroelectronics], ST18-AU1 Datasheet - Page 42

• Manufacturer Part Number: ST18-AU1
• Description: SIX-CHANNEL DOLBY AC3/MPEG2 AUDIO DECODER
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST18-AU1
9.2.3 Control registers
Three 16-bit control registers are dedicated to the DMA controller interface. These are the
general control register, the address interrupt control register and the mask sensitivity control
register. They are detailed below.
DGC: General control register
Three bits are dedicated for each DMA channel (bits 0 to 2 to channel 0, bits 4 to 6 to channel
1, bits 8 to 10 to channel 2, bits 12 to 14 to channel 3).
(Address = 0040, Reset = 0000h, Read/Write).
DAIC: Address/interrupt control register
Four bits are dedicated for each DMA channel (bits 0 to 3 to channel 0, bits 4 to 7 to channel
1, bits 8 to 11 to channel 2, bits 12 to 15 to channel 3).
(Address = 0042, Reset = 0000h, Read/Write)
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DAI3 DLA3 DIP3 DIE3 DAI2 DLA2 DIP2 DIE2 DAI1 DLA1 DIP1 DIE1 DAI0 DLA0 DIP0 DIE0
Bit
DBC1/DBC0 Bus choice for data transfer
DRWi
Bit
DIEi
DIPi
15
15
-
DRW
14
14
3
DBC
13
13
1
Function
Data transfer direction
Function
Enable interrupt
Interrupt pending
00: X-bus (default)
01: Y-bus
10: I-bus
11: reserved
0: Write access (default)
1: Read access
0: Interrupt request output associated to channel i is masked (default)
1: Interrupt request output associated to channel i is not masked
0: No pending interrupt on channel i (default)
1: Pending interrupt on channel i (enabled if DIP_ENA input is high)
DBC
12
12
0
11
11
-
DRW
10
10
2
DBC
9
1
9
DBC
8
0
8
7
-
7
DRW
6
1
6
DBC
5
1
5
DBC
4
0
4
3
-
3
DRW
2
0
2
DBC
1
1
1
DBC
0
0
0