PLL202-14 PhaseLink (PLL), PLL202-14 Datasheet - Page 7

• Manufacturer Part Number: PLL202-14
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., Power Mgt, Wdt, Drive Ctrl, SST
• Manufacturer: PhaseLink (PLL)

5. BYTE 4: Linear Programming Register (1=Enable, 0=Disable)
6. BYTE 5: Peripheral Clock Register (1=Enable, 0=Disable)
7. BYTE 6: Reserved Register (For PLL103-02 DDR)
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Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
Pin#
44
45
47
48
-
-
-
-
Default
X
1
1
1
1
1
1
1
Pin#
Pin#
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Programmable Clock Generator for VIA Apollo Pro-266
Description
Inverted Power-up latched FS4 value(Read) / WDT Fall-back Frequency selection for FS4
Reserved ( Active/Inactive )
APIC1 ( Active/Inactive )
APIC0 ( Active/Inactive )
Reserved ( Active/Inactive )
Reserved ( Active/Inactive )
REF1 ( Active/Inactive )
REF0 ( Active/Inactive )
Default
Default
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Description
Linear programming sign bit ( 0 is “ ”, 1 is “ ” )
Linear programming magnitude bit 6 (MSB)
Linear programming magnitude bit 5
Linear programming magnitude bit 4
Linear programming magnitude bit 3
Linear programming magnitude bit 2
Linear programming magnitude bit 1
Linear programming magnitude bit 0 (LSB)
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PLL202-14
Rev 3/23/01 Page 7