PLL202-14 PhaseLink (PLL), PLL202-14 Datasheet - Page 10

• Manufacturer Part Number: PLL202-14
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., Power Mgt, Wdt, Drive Ctrl, SST
• Manufacturer: PhaseLink (PLL)

BUILT-IN WATCHDOG TIMER (WDT)
Watchdog timer is used to perform safe recovery if frequency switching causes system to enter into
“Hang-up” state within a reasonable period of time (or Watchdog time interval). The watchdog time
interval can be programmed between 0 and 63 seconds with increment of 1 second by setting the value
of I2C.Byte8.Bit(5:0). Once Enabled, WDT has to be disabled within a period that is shorter than the
programmed watchdog interval; otherwise WDT will generate a 500ms low watchdog reset pulse to
provoke a system reset. After system restarts, the PLL202-14 will start from predefined Fall-back
Frequency (the value of I2C Byte1.Bit(4,6,7), Byte3.Bit7, Byte5.Bit7). If system for any reason fails again
at Fall-back Frequency, the internal hardware will then generate a watchdog reset to restart the system
from the value of external hardware jumper setting to ensure a safe recovery.
Example usage:
1. System power-up at CPU= 66.8MHz (Group A) where external jumpers are used.
2A. Switch to target CPU=100.2MHz frequency (Group B) with following I2C register setting:
2B. Switch to target CPU=79MHz within the same timing Group
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The fall-back frequency is set to the same location as that of FSEL since
frequency switching between different timing groups will cause system to hang
up. After WD timer expired or 15 seconds, the system will restart properly at
target 100.2MHz if CPU is capable; otherwise WDT will perform another reset
action to restart the system from 66.8 MHz
The fall-back frequency is recommended to set at the most safe and comfortable
level to ensure a successful reboot such as 75.0 if system is unable to switch to
79Mhz.
FS3 FS2 FS1 FS0 CTR FS4
Sign M6
ENB
7
7
7
7
1 1 0 1 1 0 0 0
0 0 0 0 0 0 0 0
1 0 0 0 1 1 1 1
0 0 0 0 1 1 0 1
6
6
6
6
M5
T5
5
5
5
5
M4
T4
FB4 FB3 FB2 FB1 FB0
4
4
4
4
Programmable Clock Generator for VIA Apollo Pro-266
M3
T3
3
3
3
3
M2
T2
2
2
2
2
M1
T1
1
1
1
1
M0
T0
0
0
0
0
FSEL
M =0
WD-Timer = 15s Setting in I2C.BYTE8
FBSEL
Setting in I2C.BYTE0
Setting in I2C.BYTE7
Setting in I2C.BYTE1, 3, 5
PLL202-14
Rev 3/23/01 Page 10