PLL202-14 PhaseLink (PLL), PLL202-14 Datasheet - Page 9

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PLL202-14

Manufacturer Part Number
PLL202-14
Description
Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., Power Mgt, Wdt, Drive Ctrl, SST
Manufacturer
PhaseLink (PLL)
Datasheet
PROGRAMMING OF CPU FREQUENCY
To simplify traditional loop counter setting, the PLL202-14 device incorporates SMART-BYTE ™
technology with a single byte programming via I2C to better optimize clock jitter and spread spectrum
performance. Detail of PLL202-14's dual mode frequency programming method is described below:
1. ROM-table Frequency Programming:
2. Fine-step Linear Frequency Programming:
FREQUENCY PROGRAMMING EXAMPLE:
1. Procedures to program target CPU frequency to 122.0 Mhz in Group B timing:
A. Locate the closest CPU frequency from Frequency from Frequency-ROM table: 118.0
B.
C. Solve M (Linear Magnitude factor) in integer:
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
The pre-defined 32 frequencies found in Frequency table can be accessed either through 5 external
jumpers or by setting internal I2C register in BYTE0.
CPU Frequency can be programmed via I2C in fine and linear positive or negative stepping around
current selected CPU frequency in Frequency table. The highest step is either +127 or -127. Other
bus frequencies will be changed proportionally with the rate that CPU frequency change. The formula
is as follow:
D.
= 0.15 for Group B
Program I2C register:
F
F
F
PCI
CPU
AGP
FS3 FS2 FS1 FS0 CTR FS4
Sign M6
7
7
1 1 1 0 1 0 0 0
0 0 0 1 1 0 1 1
M = (F
6
6
= (122
= 27
= 78.6 * (1 + 0.04%) = 78.63
= 118.0 + (0.15) * 27 = 122.05 ( % of frequency increased = 0.04% )
= 39.3 * (1 + 0.04%) = 39.32
M5
5
5
CPU
Where:
M4
4
4
Programmable Clock Generator for VIA Apollo Pro-266
118) / 0.15
F
CPU-ROMTABLE
M3
3
3
F
CPU
M2
1. M is magnitude factor defined in I2C Byte4.bit (0:6)
2.
3.
2
2
=
M1
1
1
(sign bit) of M is defined in I2C Byte4.bit 7
is a constant but related to CPU's three Timing groups definition
= 0.11 (for Group A),
F
) /
M0
0
0
CPU-ROM-table
Setting of M = +27 in I2C.BYTE4
Setting of I2C.BYTE0
(=0.22, 0.15 or 0.11)
= 0.15 (for Group B, C) or
*
M
PLL202-14
= 0.22 (for Group D)
Rev 3/23/01 Page 9

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