PLL202-14 PhaseLink (PLL), PLL202-14 Datasheet - Page 8

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PLL202-14

Manufacturer Part Number
PLL202-14
Description
Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., Power Mgt, Wdt, Drive Ctrl, SST
Manufacturer
PhaseLink (PLL)
Datasheet
8. BYTE 7: Reserved Register (For PLL103-02 DDR)
9. BYTE 8: Watchdog Timer / Revision ID and Vendor ID Register (1=Enable, 0=Disable)
Note: *: Default value at power-up. Don’t write into this register, writing into this register can cause malfunction.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
Pin#
Pin#
Programmable Clock Generator for VIA Apollo Pro-266
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Default
Default
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Watchdog Timer Enable Bit. 1=Enable, 0=Disable
Revision ID Bit 2*
Watchdog Time Interval Bit 5 (MSB)
Watchdog Time Interval Bit 4
Watchdog Time Interval Bit 3
Watchdog Time Interval Bit 2
Watchdog Time Interval Bit 1
Watchdog Time Interval Bit 0 (LSB)
Description
Description
PLL202-14
Revision ID Bit 1*
Revision ID Bit 0*
Vendor ID Bit 3*
Vendor ID Bit 2*
Vendor ID Bit 1*
Vendor ID Bit 0*
Rev 3/23/01 Page 8

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