mx98713 Macronix International Co., mx98713 Datasheet - Page 12

• Manufacturer Part Number: mx98713
• Description: 100/10base Pci Mac Controller
• Manufacturer: Macronix International Co.

The bit content will be reset to 0 when a 1 is written to the corresponding bit location.
bit 0 : IO Space Access, set to 1 to enable IO access
bit 1: Memory Space Access, set to 1 to enable memory access
bit 2: Master Operation, set to 1 to support bus master mode
bit 3: bit 5 :not used
bit 6: Parity Error Response, set to 1 to enable the PMAC to assert PERR# if parity error detected.
bit 7: not used
bit 8: System Error Enable, set to 1 to enable the PMAC to assert SERR# when parity error is detected on
bit 22 - bit 9: not used
bit 23: Fast Back-to-back, always set by the PMAC to accept fast back-to-back transactions that are not sent
bit 24: Data Parity Report, is set to 1 by the PMAC only if PMAC is bus master, it sends or causes
biut 26 -bit 25: Device Select Timing, fixed at 01 which indicates a medium assertion speed of DEVSEL#.
bit 27: not used
bit 28: Receive Target Abort, is set to indicate the PMAC master transaction is terminated by a target abort.
bit 29: Receive Master Abort, is set to indicate the PMAC terminated a master transaction with Master abort
bit 30: Signal System Error, is set to indicate the PMAC asserted SERR#.
bit 31: Detected Parity Error, is set whenever a parity error detected regardless of PFCS<6>.
bit 3 - bit 0 : Step Number, fixed to 0h and incremented for subsequent steps of the version.
bit 7 - bit 4 : Revision Number, fixed to 0h and is incremented for subsequent revisions.
bit 15 - bit 8 : not used
bit 23 - bit 16 : Subclass, fixed to 0h.
bit 31 - bit 24 : Base Class, fixed to 2h.
PFRV Register ( 0Bh-08h)
Revision Number
5.1.4. PCI REVISION REGISTER ( PFRV )
Step Number
address lines and CBE[3:0]# .
PERR# active and PFCS<6> is also set.
to the same bus device.
Base Class
Subclass
12
MX98713
INDEX