mx98713 Macronix International Co., mx98713 Datasheet - Page 5

• Manufacturer Part Number: mx98713
• Description: 100/10base Pci Mac Controller
• Manufacturer: Macronix International Co.

4. MX98713 PIN DESCRIPTIONS
Pin Name TYPE
DEVSEL#
CBE[3:0]
AD[31:0]
FRAME#
PCICLK
TRDY#
IRDY#
IDSEL
INTA#
RST#
O/D
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
PCI address/data bus: shared PCI address/data bus lines. Both little or big
ending byte ordering are supported.
PCI command and byte enable bus: shared PCI command byte enable bus;
during the address phase of the transaction, these four bits provide the bus
command. During the data phase, these four bits provide the byte enable.
PCI FRAME# signal: shared PCI cycle start signal, asserted to indicate the
beginning of a bus transaction. While frame# is asserted, data transfers continue.
PCI Target ready: issued by the target agent, a data phase is completed on the
rising edge of PCICLK when both IRDY# and TRDY# are asserted.
PCI Master ready: indicates the ability of bus master to complete the current
data phase of the transaction. A data phase is completed on any rising edge of
PCICLK when both IRDY# and TRDY# are asserted.
PCI slave device select: asserted by the target of the current bus access.
When the MX98713 is the initiator of current bus access, the target must assert
DEVSEL# within 5 bus cycles; otherwise, the cycle will be aborted.
PCI initialization device select: target specific device select signal for
configuration cycles issued by host
PCI bus clock input: PCI bus clock targeted at 33MHZ
PCI bus reset: host system hardware reset
PCI bus interrupt request signal: wired to INTA# lines
Function and Driver Descriptions
5
MX98713
INDEX