mx98713 Macronix International Co., mx98713 Datasheet - Page 17

• Manufacturer Part Number: mx98713
• Description: 100/10base Pci Mac Controller
• Manufacturer: Macronix International Co.

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Field Name
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0
1
6:2
7
13:8
15:14 CAL
18:17 TAP
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5.2.1. BUS MODE REGISTER ( CSR0 )
SWR
BAR
DSL
BLE
PBL
TAP - Transmit Automatic Polling
ZERO - Must be zero
CAL - Cache Alignment
PBL - Programmable Burst Length
BLE - Big/Little Ending
DSL - Descriptor Skip Length
BAR - Bus Arbitration
SWR - Software Reset
Description
Software Reset, when set, PMAC resets all internal hardware with the exception of the
configuration area and port selection.
Bus Arbitration, when set, a round-robin arbitration scheme is applied resulting in equal
sharing of internal bus. When reset, receive channel has higher priority over transmit channel
in case of possible danger of receive FIFO overrun situation.
Descriptor Skip Length, specifies the number of long words to skip between two descriptors
for implicit chained structure.
Big/Little Endian, set for big endian byte ordering mode, reset for little endian byte ordering
mode
Programmable Burst Length, specifies the maximum number of long words to be transferred
in one DMA transaction. default is 0 which means 4 double words, possible values can be
1,2,4,8,16 or 32.
Cache Alignment, programmable address boundaries of data burst stop, PMAC can handle
non-cache-aligned fragment as well as cache-aligned fragment efficiently.
Transmit Auto-Polling time interval, defines the time interval for PMAC to performs transmit
polling command automatically at transmit suspended state.
17
0
MX98713
INDEX