CY7C1480V33 Cypress Semiconductor, CY7C1480V33 Datasheet - Page 16

• Manufacturer Part Number: CY7C1480V33
• Description: (CY7C1480V33 / CY7C1482V33 / CY7C1486V33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
• Manufacturer: Cypress Semiconductor

Document #: 38-05283 Rev. *C
Scan Register Sizes
Identification Codes
Boundary Scan Order (x36)
Instruction
Bypass
ID
Boundary Scan Order-165FBGA
Boundary Scan Order-209BGA
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Instruction
Bit #
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
11
1
2
3
4
5
6
7
8
9
Register Name
165-Ball ID
Code
100
000
001
010
011
101
110
111
G1
G2
M1
M2
C1
D1
E1
D2
E2
K1
N1
K2
R1
R2
R3
P2
R4
P6
R6
F1
F2
J1
L1
J2
L2
Captures the I/O ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
PRELIMINARY
Bit Size (x36)
Boundary Scan Order (x36)
32
73
3
1
-
Bit #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Description
Bit Size (x18)
165-Ball ID
32
54
3
1
-
M11
M10
P10
R10
R11
N11
K10
H11
G11
D10
P11
L11
L10
K11
J10
F11
E11
J11
N6
R8
P3
P4
P8
P9
R9
CY7C1482V33
CY7C1486V33
CY7C1480V33
(continued)
Bit Size (x72)
Page 16 of 30
112
32
3
1
-