CY7C1480V33 Cypress Semiconductor, CY7C1480V33 Datasheet - Page 8

• Manufacturer Part Number: CY7C1480V33
• Description: (CY7C1480V33 / CY7C1482V33 / CY7C1486V33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
• Manufacturer: Cypress Semiconductor

Document #: 38-05283 Rev. *C
Pin Definitions
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
(250-MHz device).
The CY7C1480V33/CY7C1482V33/CY7C1486V33 supports
secondary cache in systems utilizing either a linear or inter-
leaved burst sequence. The interleaved burst order supports
Pentium and i486™ processors. The linear burst sequence is
suited for processors that utilize a linear burst sequence. The
burst order is user selectable, and is determined by sampling
the MODE input. Accesses can be initiated with either the
Processor Address Strobe (ADSP) or the Controller Address
Strobe (ADSC). Address advancement through the burst
sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored
if CE
(A) is stored into the address advancement logic and the
Address Register while being presented to the memory array.
The corresponding data is allowed to propagate to the input of
the Output Registers. At the rising edge of the next clock the
data is allowed to propagate through the output register and
onto the data bus within 3.0 ns (250-MHz device) if OE is
active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its
outputs are always tri-stated during the first cycle of the
Pin Name
TDO
TDI
TMS
TCK
NC
1
, CE
1
is HIGH. The address presented to the address inputs
2
, CE
3
are all asserted active, and (3) the Write
(continued)
Synchronous
Synchronous
Synchronous
JTAG Serial
JTAG Serial
JTAG Serial
JTAG Clock
Output
Input
Input
I/O
-
X
) inputs. A Global Write
1
, CE
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not being utilized, this pin should be disconnected. This pin is not
available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be disconnected or connected to V
is not available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be disconnected or connected to V
is not available on TQFP packages.
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin
must be connected to V
No Connects. Not internally connected to the die
2
, CE
CO
) is 3.0 ns
PRELIMINARY
3
) and an
1
SS
access. After the first cycle of the access, the outputs are
controlled by the OE signal. Consecutive single Read cycles
are supported. Once the SRAM is deselected at clock rise by
the chip select and either ADSP or ADSC signals, its output
will tri-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BW
ADV inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BW
signals.
The CY7C1480V33/CY7C1482V33/CY7C1486V33 provides
Byte Write capability that is described in the Write Cycle
Descriptions table. Asserting the Byte Write Enable input
(BWE) with the selected Byte Write (BW
tively write to only the desired bytes. Bytes not selected during
a Byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.
Because CY7C1480V33/CY7C1482V33/CY7C1486V33 is a
common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQs inputs.
Doing so will tri-state the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE
and (4) the appropriate combination of the Write inputs (GW,
BWE, and BW
desired byte(s). ADSC-triggered Write accesses require a
single clock cycle to complete. The address presented to A is
loaded
advancement logic while being delivered to the memory array.
. This pin is not available on TQFP packages.
1
, CE
into
Description
2
, CE
X
the
) are asserted active to conduct a Write to the
3
address
are all asserted active. The address
1
, CE
2
register
, CE
3
CY7C1482V33
CY7C1486V33
CY7C1480V33
are all asserted active,
and
X
) input, will selec-
the
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DD
DD
. This pin
. This pin
address
X
) and
X