CY7C1480V33 Cypress Semiconductor, CY7C1480V33 Datasheet - Page 23

• Manufacturer Part Number: CY7C1480V33
• Description: (CY7C1480V33 / CY7C1482V33 / CY7C1486V33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
• Manufacturer: Cypress Semiconductor

Document #: 38-05283 Rev. *C
Switching Waveforms
Write Cycle Timing
Note:
22. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
Data Out (Q)
Data In (D)
ADDRESS
ADSP
ADSC
BWE,
ADV
BW
CLK
GW
OE
CE
X
BURST READ
High-Z
t ADS
[21, 22]
t CES
t AS
A1
t ADH
t CEH
t AH
t CH
t
OEHZ
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t CYC
t ADS
(continued)
t CL
t DS
Single WRITE
D(A1)
t ADH
t DH
A2
D(A2)
PRELIMINARY
DON’T CARE
t WES
D(A2 + 1)
BURST WRITE
t WEH
UNDEFINED
D(A2 + 1)
X
LOW.
ADV suspends burst
D(A2 + 2)
ADSC extends burst
D(A2 + 3)
t ADS
A3
D(A3)
t ADH
CY7C1482V33
CY7C1486V33
CY7C1480V33
t
ADVS
t WES
Extended BURST WRITE
D(A3 + 1)
t
t WEH
ADVH
Page 23 of 30
D(A3 + 2)