MC68HC705C Motorola, MC68HC705C Datasheet - Page 149

• Manufacturer Part Number: MC68HC705C
• Description: HCMOS Microcontroller Unit
• Manufacturer: Motorola

11.9.3 SPI Status Register
MC68HC705C8A — Rev. 2.0
MOTOROLA
Address:
The SPSR shown in
conditions:
SPIF — SPI Flag
WCOL — Write Collision Bit
Reset:
Read:
Write:
•
•
•
This clearable, read-only bit is set each time a byte shifts out of or into
the shift register. SPIF generates an interrupt request if the SPIE bit
in the SPCR is also set. Clear SPIF by reading the SPSR with SPIF
set and then reading or writing the SPDR. Reset clears the SPIF bit.
This clearable, read-only flag is set when software writes to the SPDR
while a transmission is in progress. Clear the WCOL bit by reading the
SPSR with WCOL set and then reading or writing the SPDR. Reset
clears WCOL.
1 = Transmission complete
0 = Transmission not complete
1 = Invalid write to SPDR
0 = No invalid write to SPDR
SPI transmission complete
Write collision
Mode fault
$000B
SPIF
Bit 7
0
Serial Peripheral Interface (SPI)
Figure 11-9. SPI Status Register (SPSR)
= Unimplemented
WCOL
6
0
Figure 11-9
5
MODF
contains flags to signal these
4
0
3
Serial Peripheral Interface (SPI)
2
SPI I/O Registers
1
Technical Data
Bit 0
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