CY7C1355C-100AC CYPRESS [Cypress Semiconductor], CY7C1355C-100AC Datasheet - Page 13

• Manufacturer Part Number: CY7C1355C-100AC
• Description: 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05539 Rev. **
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1355C/CY7C1357C incorporates a serial boundary
scan test access port (TAP). This part is fully compliant with
1149.1. The TAP operates using JEDEC-standard 3.3V or
2.5V I/O logic levels.
The CY7C1355C/CY7C1357Ccontains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(V
internally pulled up and may be unconnected. They may alter-
nately be connected to V
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
TAP Controller State Diagram
The 0/1 next to each state represents the value of TMS at the
rising edge of the TCK.
1
0
TEST-LOGIC
RUN-TEST/
SS
RESET
IDLE
0
) to prevent clocking of the device. TDI and TMS are
1
1
0
DD
CAPTURE-DR
UPDATE-DR
PAUSE-DR
DR-SCAN
SHIFT-DR
EXIT1-DR
EXIT2-DR
1
SELECT
0
0
1
0
1
1
through a pull-up resistor. TDO
0
1
1
0
0
1
0
CAPTURE-IR
UPDATE-IR
PAUSE-IR
1
EXIT1-IR
EXIT2-IR
IR-SCAN
SHIFT-IR
SELECT
0
0
1
0
1
1
PRELIMINARY
0
1
1
0
0
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
CY7C1355C
CY7C1357C
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