CY7C1355C-100AC CYPRESS [Cypress Semiconductor], CY7C1355C-100AC Datasheet - Page 26

• Manufacturer Part Number: CY7C1355C-100AC
• Description: 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05539 Rev. **
Switching Waveforms
Read/Write Waveforms
Notes:
26. For this waveform ZZ is tied LOW.
27. When CE is LOW, CE
28. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
COMMAND
ADDRESS
ADV/LD
BW
CEN
CLK
WE
DQ
OE
CE
X
t CENS
t CES
t AS
WRITE
D(A1)
1
A1
1
is LOW, CE
t CENH
t CEH
t AH
[26, 27, 28]
t DS
WRITE
D(A1)
D(A2)
2
A2
is HIGH and CE
2
t CH
t DH
t CYC
t CL
D(A2+1)
BURST
WRITE
D(A2)
3
3
is LOW. When CE is HIGH, CE
DON’T CARE
PRELIMINARY
D(A2+1)
READ
Q(A3)
A3
4
t CDV
t CLZ
Q(A4)
READ
Q(A3)
A4
5
t DOH
t OEHZ
1
UNDEFINED
is HIGH or CE
Q(A4+1)
BURST
Q(A4)
READ
6
t OEV
t OELZ
2
is LOW or CE
Q(A4+1)
WRITE
D(A5)
A5
7
t CHZ
t DOH
3
is HIGH.
Q(A6)
READ
A6
D(A5)
8
CY7C1355C
CY7C1357C
WRITE
D(A7)
Q(A6)
A7
9
Page 26 of 33
DESELECT
D(A7)
10