CY7C1355C-100AC CYPRESS [Cypress Semiconductor], CY7C1355C-100AC Datasheet - Page 16

• Manufacturer Part Number: CY7C1355C-100AC
• Description: 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05539 Rev. **
TAP Timing
TAP AC Switching Characteristics
3.3V TAP AC Test Conditions
Input pulse levels ........ ........................................V
Input rise and fall times ..................... ..............................1 ns
Input timing reference levels ...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Clock
t
t
t
t
Output Times
t
t
Set-up Times
t
t
t
Hold Times
t
t
t
Notes:
10. t
11. Test conditions are specified using the load in TAP AC Test Conditions. t
Parameter
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
CS
and t
CH
refer to the set-up and hold time requirements of latching data from the boundary scan register.
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
TMS Set-Up to TCK Clock Rise
TDI Set-Up to TCK Clock Rise
Capture Set-Up to TCK Rise
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
Test Mode Select
Test Data-Out
Test Data-In
Test Clock
(TDO)
(TMS)
(TCK)
(TDI)
1
Description
Over the operating Range
t TMSS
t TDIS
SS
PRELIMINARY
2
to 3.3V
t TMSH
t TDIH
t TH
DON’T CARE
R
/t
t
F
TL
= 1 ns.
3
3.3V TAP AC Output Load Equivalent
[10, 11]
t CYC
TDO
UNDEFINED
4
t TDOX
Z = 50
O
t TDOV
5
Min.
50
25
25
0
5
5
5
5
5
5
1.5V
6
Max.
CY7C1355C
CY7C1357C
20
5
20pF
50
Page 16 of 33
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns