CY7C1355C-100AC CYPRESS [Cypress Semiconductor], CY7C1355C-100AC Datasheet - Page 27

• Manufacturer Part Number: CY7C1355C-100AC
• Description: 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05539 Rev. **
Switching Waveforms
NOP, STALL AND DESELECT Cycles
Note:
29. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
COMMAND
ADDRESS
ADV/LD
BW
CEN
CLK
WE
DQ
OE
CE
X
t CENS
t CES
t AS
WRITE
D(A1)
A1
1
t CENH
t CEH
t AH
t DS
(continued)
WRITE
D(A1)
D(A2)
A2
2
t CH
t DH
t CYC
t CL
[26, 27, 29]
D(A2+1)
BURST
WRITE
D(A2)
3
DON’T CARE
D(A2+1)
PRELIMINARY
READ
Q(A3)
A3
4
t CDV
t CLZ
Q(A4)
READ
Q(A3)
A4
5
t DOH
t OEHZ
UNDEFINED
Q(A4+1)
BURST
Q(A4)
READ
6
t OEV
t OELZ
WRITE
Q(A4+1)
D(A5)
A5
7
t CHZ
t DOH
READ
Q(A6)
A6
D(A5)
8
CY7C1355C
CY7C1357C
WRITE
D(A7)
Q(A6)
A7
9
Page 27 of 33
DESELECT
D(A7)
10