ADV7390BCPZ-REEL AD [Analog Devices], ADV7390BCPZ-REEL Datasheet - Page 12

• Manufacturer Part Number: ADV7390BCPZ-REEL
• Description: Low Power, Chip Scale 10-Bit SD/HD Video Encoder
• Manufacturer: AD [Analog Devices]

ADV7390/ADV7391/ADV7392/ADV7393
PIXEL PORT
a(MIN) = 244 CLOCK CYCLES FOR 525p.
a(MIN) = 264 CLOCK CYCLES FOR 625p.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
PIXEL PORT*
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
PIXEL PORT
Y OUTPUT
Y OUTPUT
SPECIFICATION SECTION OF THE DATA SHEET.
SPECIFICATION SECTION OF THE DATA SHEET.
HSYNC
VSYNC
HSYNC
VSYNC
Figure 11. ED-DDR, 8-/10-Bit 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram
Figure 10. ED-SDR, 16-Bit 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram
b
b
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a
a
Cb0
Y0
Cb0
Cr0
Y1
Y0
Cb2
Y2
Cr0
Cr2
Y3
Y1