ADV7390BCPZ-REEL AD [Analog Devices], ADV7390BCPZ-REEL Datasheet - Page 42

• Manufacturer Part Number: ADV7390BCPZ-REEL
• Description: Low Power, Chip Scale 10-Bit SD/HD Video Encoder
• Manufacturer: AD [Analog Devices]

ADV7390/ADV7391/ADV7392/ADV7393
ADV7392/ADV7393 INPUT CONFIGURATION
The ADV7392/ADV7393 supports a number of different input
modes. The desired input mode is selected using Subaddress 0x01,
Bits[6:4]. The ADV7392/ADV7393 defaults to standard
definition (SD) mode upon power-up. Table 31 provides an
overview of all possible input configurations. Each input mode
is described in detail in this section.
STANDARD DEFINITION
Subaddress 0x01, Bits[6:4] = 000
SD YCrCb data can be input in 4:2:2 format over an 8-, 10-, or 16-
bit bus. SD RGB data can be input in 4:4:4 format over a 16-bit bus.
A 27 MHz clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
the HSYNC and VSYNC pins. Embedded EAV/SAV timing
codes are also supported in 8-bit and 10-bit modes.
8-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0
Subaddress 0x88, Bits[4:3] = 00
In 8-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin P15 to Pin P8, with P8 being the LSB. The ITU-R
BT.601/656 input standard is supported.
10-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0
Subaddress 0x88, Bits[4:3] = 10
In 10-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin P15 to Pin P6, with P6 being the LSB. The ITU-R
BT.601/656 input standard is supported.
Table 31. ADV7392/ADV7393 Input Configuration
Input Mode
000
001
010
111
1
2
3
4
The input mode is determined by Subaddress 0x01, Bits[6:4].
In SD mode, the width of the input data is determined by Subaddress 0x88, Bits[4:3].
External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported.
ED = enhanced definition = 525p and 625p.
SD
ED/HD-SDR (16-Bit)
ED/HD-DDR
ED (At 54 MHz)
8-Bit
10-Bit
16-Bit
16-Bit
8-Bit
10-Bit
8-Bit
10-Bit
2
1
3
3
4
P15
P14
P13
B
P12
YCrCb
YCrCb
YCrCb
Y
Y
Rev. 0 | Page 42 of 96
P11
YCrCb
YCrCb
YCrCb
SD RGB Input Enable (0x87[7]) = 0
SD RGB Input Enable (0x87[7]) = 1
ED/HD Input Format (0x33[2]) = 0
ED/HD Input Format (0x33[2]) = 1
ED/HD Input Format (0x33[2]) = 0
ED/HD Input Format (0x33[2]) = 1
P10
16-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0
Subaddress 0x88, Bits[4:3] = 01
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin P15 to Pin P8, with P8 being the LSB.
The CrCb pixel data is input on Pin P7 to Pin P0, with P0 being
the LSB.
The pixel data is updated at half the rate of the clock, that is, at a
rate of 13.5 MHz (see Figure 3).
16-Bit 4:4:4 RGB Mode
Subaddress 0x87, Bit 7 = 1
In 16-bit 4:4:4 RGB input mode, the red pixel data is input on
Pin P4 to Pin P0, the green pixel data is input on Pin P10 to
Pin P5, and the blue pixel data is input on Pin P15 to Pin P11.
P0, P5, and P11 are the respective bus LSBs.
The pixel data is updated at half the rate of the clock, that is, at a
rate of 13.5 MHz (see Figure 4).
P9
P8
DECODER
MPEG2
G
P7
Figure 54. SD Example Application
YCrCb
P6
27MHz
8/10
2
P5
CLKIN
P[15:8]/P[15:6]
HSYNC
P4
VSYNC,
ADV7392/
ADV7393
CrCb
CrCb
P3
P2
R
P1
P0