ADV7390BCPZ-REEL AD [Analog Devices], ADV7390BCPZ-REEL Datasheet - Page 61

• Manufacturer Part Number: ADV7390BCPZ-REEL
• Description: Low Power, Chip Scale 10-Bit SD/HD Video Encoder
• Manufacturer: AD [Analog Devices]

LOW POWER MODE
Subaddress 0x0D, Bits[2:0]
For power sensitive applications, the ADV739x supports an
Analog Devices, Inc. proprietary low power mode of operation.
To utilize this low power mode, the DACs must be operating in
full-drive mode (R
not available in low drive mode (R
Low power mode can be independently enabled or disabled on
each DAC using Subaddress 0x0D, Bits[2:0]. Low power mode
is disabled by default on all DACs.
In low power mode, DAC current consumption is content
dependent, and on a typical video stream, it can be reduced by
as much as 40%. For applications requiring the highest possible
video performance, low power mode should be disabled.
CABLE DETECTION
Subaddress 0x10, Bits[1:0]
The ADV739x includes an Analog Devices, Inc. proprietary
cable detection feature.
The cable detection feature is available on DAC 1 and DAC 2
when operating in full-drive mode (R
assuming a connected cable). The feature is not available in low-
drive mode (R
monitored, the DAC must be powered up in Subaddress 0x00.
The cable detection feature can be used with all SD, ED, and
HD video standards. It is available for all output configurations,
that is, CVBS, YC, YPrPb, and RGB output configurations.
For CVBS/YC output configurations, both DAC 1 and DAC 2
are monitored, that is, the CVBS and YC luma outputs are
monitored. For YPrPb and RGB output configurations, only
DAC 1 is monitored, that is, the luma or green output is
monitored.
Once per frame, the ADV739x monitors DAC 1 and/or DAC 2,
updating Subaddress 0x10, Bit 0 and/or Bit 1, respectively. If a
cable is detected on one of the DACs, the relevant bit is set to 0.
If not, the bit is set to 1.
DAC AUTO POWER-DOWN
Subaddress 0x10, Bit 4
For power sensitive applications, a DAC auto power-down
feature can be enabled using Subaddress 0x10, Bit 4. This
feature is only available when the cable detection feature is
enabled.
With this feature enabled, the cable detection circuitry monitors
DAC 1 and/or DAC 2 once per frame, and if they are
unconnected, automatically powers down some or all of the
DACs. Which DAC or DACs are powered down depends on the
selected output configuration.
SET
= 4.12 kΩ, R
SET
= 510 Ω, R
L
= 300 Ω). For a DAC to be
L
= 37.5 Ω). Low power mode is
SET
= 4.12 kΩ, R
SET
= 510 Ω, R
L
= 300 Ω).
L
= 37.5 Ω,
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For CVBS/YC output configurations, if DAC 1 is unconnected,
only DAC 1 powers down. If DAC 2 is unconnected, DAC 2 and
DAC 3 power down.
For YPrPb and RGB output configurations, if DAC 1 is
unconnected, all three DACs are powered down. DAC 2 is not
monitored for YPrPb and RGB output configurations.
Once per frame, DAC 1 and/or DAC 2 are monitored. If a cable
is detected, the appropriate DAC or DACs remain powered up
for the duration of the frame. If no cable is detected, the
appropriate DAC or DACs power down until the next frame,
when the process is repeated.
PIXEL AND CONTROL PORT READBACK
Subaddress 0x13, Subaddress 0x14, Subaddress 0x16
The ADV739x supports the readback of most digital inputs via
the I
connectivity testing with upstream devices.
The pixel port (P[15:0] or P[7:0]), HSYNC , VSYNC , and
SFL/MISO are available for readback via the MPU port.
The readback registers are located at Subaddress 0x13,
Subaddress 0x14, and Subaddress 0x16.
When using this feature, a clock signal should be applied to the
CLKIN pin to register the levels applied to the input pins.
The SD input mode (Subaddress 0x01, Bits[6:4] = 000) must be
selected when using this feature.
RESET MECHANISMS
Subaddress 0x17, Bit 1
A hardware reset is activated with a high-to-low transition on
the RESET pin in accordance with the timing specifications.
This resets all registers to their default values. After a hardware
reset, the MPU port is configured for I
device operation, a hardware reset is necessary after power-up.
The ADV739x also has a software reset accessible via the
I
to Subaddress 0x17, Bit 1. This resets all registers to their
default values. This bit is self-clearing, that is, after a 1 has been
written to the bit, the bit automatically returns to 0.
When operating in SPI mode, a software reset does not cause
the device to revert to I
reset via the RESET pin or a power-down needs to occur.
A hardware reset is necessary after power-up for correct device
operation. If no hardware reset functionality is required by the
application, the RESET pin can be connected to a RC network
to provide the hardware reset necessary after power-up. After
power-up, the time constant of the RC network holds the
RESET pin low for long enough to cause a reset to take place.
All subsequent resets can be done via software.
2
C/SPI MPU port. A software reset is activated by writing a 1
ADV7390/ADV7391/ADV7392/ADV7393
2
C/SPI MPU port. This feature is useful for board-level
2
C mode. For this to occur, a hardware
2
C operation. For correct