ADV7390BCPZ-REEL AD [Analog Devices], ADV7390BCPZ-REEL Datasheet - Page 84

• Manufacturer Part Number: ADV7390BCPZ-REEL
• Description: Low Power, Chip Scale 10-Bit SD/HD Video Encoder
• Manufacturer: AD [Analog Devices]

ADV7390/ADV7391/ADV7392/ADV7393
APPENDIX 9–CONFIGURATION SCRIPTS
The scripts listed in the following pages can be used to configure the ADV739x for basic operation. Certain features are enabled by
default. If required for a specific application, further features can be enabled. Table 58 lists the scripts available for SD modes of operation.
Similarly, Table 89 and Table 106 list the scripts available for ED and HD modes of operation, respectively.
STANDARD DEFINITION
Table 58. SD Configuration Scripts
Input Format
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
Table 59. 8-Bit 525i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
0x82
Setting
0x02
0x1C
0x00
0x10
0xC9
Input Data Width
8-Bit SDR
8-Bit SDR
8-Bit SDR
8-Bit SDR
8-Bit SDR
10-Bit SDR
10-Bit SDR
10-Bit SDR
10-Bit SDR
10-Bit SDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
8-Bit SDR
8-Bit SDR
8-Bit SDR
8-Bit SDR
8-Bit SDR
10-Bit SDR
10-Bit SDR
10-Bit SDR
10-Bit SDR
10-Bit SDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
16-Bit SDR
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
Synchronization Format
EAV/SAV
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
HSYNC / VSYNC
HSYNC / VSYNC
HSYNC / VSYNC
HSYNC / VSYNC
HSYNC / VSYNC
EAV/SAV
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
HSYNC / VSYNC
HSYNC / VSYNC
HSYNC / VSYNC
HSYNC / VSYNC
HSYNC / VSYNC
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Input Color Space
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
RGB
RGB
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
RGB
RGB
Table 60. 8-Bit 525i YCrCb In (EAV/SAV), CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
0x82
Setting
0x02
0x1C
0x00
0x10
0xCB
Output Color Space
YPrPb
CVBS/Y-C (S-Video)
YPrPb
RGB
YPrPb
YPrPb
RGB
YPrPb
YPrPb
CVBS/ Y-C (S-Video)
RGB
YPrPb
CVBS/Y-C (S-Video)
YPrPb
RGB
YPrPb
YPrPb
RGB
YPrPb
YPrPb
CVBS/Y-C (S-Video)
RGB
RGB
CVBS/ Y-C (S-Video)
RGB
RGB
RGB
CVBS/Y-C (S-Video)
RGB
RGB
Description
Software reset
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/S-Video out.
SSAF PrPb filter enabled. Active video
edge control enabled. Pedestal enabled.
Table Number
Table 59
Table 60
Table 61
Table 62
Table 63
Table 64
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Table 73
Table 74
Table 75
Table 76
Table 77
Table 78
Table 79
Table 80
Table 81
Table 82
Table 83
Table 84
Table 85
Table 86
Table 87
Table 88