ADV7390BCPZ-REEL AD [Analog Devices], ADV7390BCPZ-REEL Datasheet - Page 29

• Manufacturer Part Number: ADV7390BCPZ-REEL
• Description: Low Power, Chip Scale 10-Bit SD/HD Video Encoder
• Manufacturer: AD [Analog Devices]

Table 17. Register 0x31 to Register 0x33
SR7 to
SR0
0x31
0x32
0x33
1
Available on the ADV7392/ADV7393 (40-pin devices) only.
Register
ED/HD Mode
Register 2
ED/HD Mode
Register 3
ED/HD Mode
Register 4
Bit Description
ED/HD Pixel Data Valid.
HD Oversample Rate Select.
ED/HD Test Pattern Enable.
ED/HD Test Pattern Hatch/Field.
ED/HD Vertical Blanking Interval (VBI)
Open.
ED/HD Undershoot Limiter.
ED/HD Sharpness Filter.
ED/HD Y Delay with Respect to Falling
Edge of HSYNC.
ED/HD Color Delay with Respect to
Falling Edge of HSYNC.
ED/HD CGMS Enable.
ED/HD CGMS CRC Enable.
ED/HD Cr/Cb Sequence.
Reserved.
ED/HD Input Form
Sinc Compensation Filter on DAC 1,
DAC 2, DAC 3.
Reserved.
ED/HD Chroma SSAF Filter.
Reserved.
ED/HD Double Buffering.
at.
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7
0
1
0
1
0
1
6
0
0
1
1
0
1
1
5
0
1
0
1
0
0
0
0
1
0
1
ADV7390/ADV7391/ADV7392/ADV7393
Bit Number
4
0
1
0
0
1
1
0
0
3
0
1
0
1
0
1
0
0
1
2
0
1
0
0
0
0
1
0
1
1
0
1
0
0
1
1
0
0
0
0
1
0
1
0
0
1
0
1
Register Setting
Pixel data valid off
Pixel data valid on
4×
2×
HD test pattern off
HD test pattern on
Hatch
Field/frame
Disabled
Enabled
Disabled
−11 IRE
−6 IRE
−1.5 IRE
Disabled
Enabled
0 clock cycles
1 clock cycle
2 clock cycles
3 clock cycles
4 clock cycles
0 clock cycles
1 clock cycle
2 clock cycles
3 clock cycles
4 clock cycles
Disabled
Enabled
Disabled
Enabled
Cb after falling edge of HSYNC
Cr after falling edge of HSYNC
0 must be written to this bit
8-bit input
10-bit input
Disabled
Enabled
0 must be written to this bit
Disabled
Enabled
1 must be written to this bit
Disable
Enabled
1
Reset
Value
0x00
0x00
0x68