ADV7390BCPZ-REEL AD [Analog Devices], ADV7390BCPZ-REEL Datasheet - Page 37

• Manufacturer Part Number: ADV7390BCPZ-REEL
• Description: Low Power, Chip Scale 10-Bit SD/HD Video Encoder
• Manufacturer: AD [Analog Devices]

Table 26. Register 0x8A to Register 0x98
SR7 to
SR0
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
1
SD subcarrier frequency registers default to NTSC subcarrier frequency values.
SD Timing Register 0
SD Timing Register 1
SD Closed Captioning
SD Closed Captioning
SD Closed Captioning
SD Closed Captioning
SD Pedestal Register 0
SD Pedestal Register 1
SD Pedestal Register 2
SD Pedestal Register 3
Register
Note: Applicable in
master modes only,
that is, Subaddress
0x8A, Bit 0 = 1.
SD F
SD F
SD F
SD F
SD F
SC
SC
SC
SC
SC
Register 0
Register 1
Register 2
Register 3
Phase
1
1
1
1
Bit Description
SD Slave/Master Mode.
SD Timing Mode.
Reserved.
SD Luma Delay.
SD Minimum Luma Value.
SD Timing Reset.
SD HSYNC Width.
SD HSYNC to VSYNC Delay.
SD HSYNC to VSYNC Rising
Edge Delay (Mode 1 Only).
VSYNC Width (Mode 2 Only).
HSYNC to Pixel Data Adjust.
Subcarrier Frequency Bits[7:0]
Subcarrier Frequency Bits[15:8]
Subcarrier Frequency Bits[23:16]
Subcarrier Frequency Bits[31:24]
Subcarrier Phase Bits[9:2]
Extended Data on Even Fields.
Extended Data on Even Fields.
Data on Odd Fields.
Data on Odd Fields.
Pedestal on Odd Fields.
Pedestal on Odd Fields.
Pedestal on Even Fields.
Pedestal on Even Fields.
Rev. 0 | Page 37 of 96
x
0
0
1
1
x
x
x
x
7
x
x
x
x
x
17
25
17
25
6
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
16
24
16
24
5
0
0
1
1
x
x
0
0
1
1
x
x
x
x
x
x
x
x
x
15
23
15
23
ADV7390/ADV7391/ADV7392/ADV7393
Bit Number
4
0
1
0
1
0
1
0
1
0
1
x
x
x
x
x
x
14
22
x
x
x
14
22
3
1
0
0
1
1
x
x
x
x
x
x
13
21
13
21
x
x
x
2
0
0
1
1
0
1
0
1
x
x
x
x
x
x
12
20
12
20
x
x
x
1
0
1
0
1
0
0
1
1
x
x
x
x
x
x
x
x
11
19
11
19
x
0
0
1
0
1
0
1
x
x
x
x
x
x
x
x
10
18
10
18
x
Register Setting
Slave mode
Master mode
Mode 0
Mode 1
Mode 2
Mode 3
No delay
2 clock cycles
4 clock cycles
6 clock cycles
−40 IRE
−7.5 IRE
A low-high-low transition
resets the internal SD
timing counters
t
t
t
t
t
t
t
t
t
t
1 clock cycle
4 clock cycles
16 clock cycles
128 clock cycles
0 clock cycles
1 clock cycle
2 clock cycles
3 clock cycles
Subcarrier Frequency
Bits[7:0]
Subcarrier Frequency
Bits[15:8]
Subcarrier Frequency
Bits[23:16]
Subcarrier Frequency
Bits[31:24]
Extended Data Bits[7:0]
Extended Data Bits[15:8].
Data Bits[7:0]
Data Bits[15:8]
Setting any of these bits
to 1 disables pedestal
on the line number
indicated by the bit
settings
Subcarrier Phase Bits[9:2]
a
a
a
a
b
b
b
b
c
c
= 1 clock cycle
= 4 clock cycles
= 16 clock cycles
= 128 clock cycles
= t
= t
= 0 clock cycles
= 4 clock cycles
= 8 clock cycles
= 18 clock cycles
b
b
+ 32 μs
Reset
Value
0x08
0x00
0x1F
0x7C
0xF0
0x21
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00