ADV7390BCPZ-REEL AD [Analog Devices], ADV7390BCPZ-REEL Datasheet - Page 91

• Manufacturer Part Number: ADV7390BCPZ-REEL
• Description: Low Power, Chip Scale 10-Bit SD/HD Video Encoder
• Manufacturer: AD [Analog Devices]

Table 96. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Table 97. 16-Bit 625p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Table 98. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Table 99. 10-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
Setting
0x02
0x1C
0x10
0x10
0x1C
0x01
Setting
0x02
0x1C
0x10
0x10
0x18
0x01
Setting
0x02
0x1C
0x20
0x04
0x01
Setting
0x02
0x1C
0x20
0x04
0x01
0x6C
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p @ 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p @ 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled.
Rev. 0 | Page 91 of 96
Table 100. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
Table 101. 10-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 102. 8-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
Table 103. 10-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
ADV7390/ADV7391/ADV7392/ADV7393
Setting
0x02
0x1C
0x20
0x10
0x04
0x01
Setting
0x02
0x1C
0x20
0x10
0x04
0x01
0x6C
Setting
0x02
0x1C
0x20
0x1C
0x01
Setting
0x02
0x1C
0x20
0x1C
0x01
0x6C
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
625p @ 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
625p @ 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled.