ADV7390BCPZ-REEL AD [Analog Devices], ADV7390BCPZ-REEL Datasheet - Page 41

• Manufacturer Part Number: ADV7390BCPZ-REEL
• Description: Low Power, Chip Scale 10-Bit SD/HD Video Encoder
• Manufacturer: AD [Analog Devices]

ADV7390/ADV7391 INPUT CONFIGURATION
The ADV7390/ADV7391 supports a number of different input
modes. The desired input mode is selected using Subaddress 0x01,
Bits[6:4]. The ADV7390/ADV7391 defaults to standard
definition (SD) mode upon power-up. Table 30 provides an
overview of all possible input configurations. Each input mode
is described in detail in this section.
Table 30. ADV7390/ADV7391 Input Configuration
Input Mode
000
010
111
STANDARD DEFINITION
Subaddress 0x01, Bits[6:4] = 000
SD YCrCb data can be input in an interleaved 4:2:2 format over
an 8-bit bus rate of 27 MHz.
A 27 MHz clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
the HSYNC and VSYNC pins. Embedded EAV/SAV timing
codes are also supported. The ITU-R BT.601/656 input standard
is supported.
The interleaved pixel data is input on Pin P7 to Pin P0, with P0
being the LSB.
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 010
ED or HD YCrCb data can be input in an interleaved 4:2:2
format over an 8-bit DDR bus.
The clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
the HSYNC and VSYNC pins. Embedded EAV/SAV timing
codes are also supported.
8-Bit 4:2:2 ED/HD YCrCb Mode (DDR)
In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input
on Pin P7 to Pin P0 upon either the rising or falling edge of
CLKIN. P0 is the LSB.
SD
ED/HD-DDR
ED (at 54 MHz)
DECODER
MPEG2
YCrCb
Figure 49. SD Example Application
P7
27MHz
2
8
P6
P5
CLKIN
P[7:0]
HSYNC
VSYNC,
ADV7390/
ADV7391
P4
YCrCb
YCrCb
YCrCb
P2
P2
P1
Rev. 0 | Page 41 of 96
P0
The CrCb pixel data is also input on Pin P7 to Pin P0
upon the opposite edge of CLKIN. P0 is the LSB.
Whether the Y data is clocked in upon the rising or falling edge
of CLKIN is determined by Subaddress 0x01, Bits[2:1] (see
Figure 50 and Figure 51).
ENHANCED DEFINITION (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
ED YCrCb data can be input in an interleaved 4:2:2 format over
an 8-bit bus rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes are supported. External
synchronization signals are not supported in this mode.
The interleaved pixel data is input on Pin P7 to Pin P0, with P0
being the LSB.
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.
CLKIN
P[7:0]
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
CLKIN
ADV7390/ADV7391/ADV7392/ADV7393
P[7:0]
CLKIN
P[7:0]
Figure 50. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
Figure 51. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
3FF
Figure 53. ED (At 54 MHz) Input Sequence (EAV/SAV)
3FF
INTERLACED TO
3FF
PROGRESSIVE
DECODER
Figure 52. ED/HD-DDR Example Application
MPEG2
YCrCb
00
00
00
00
00
00
YCrCb
XY
XY
2
XY
8
Cb0
Cb0
Y0
HSYNC
CLKIN
P[7:0]
VSYNC,
ADV7390/
ADV7391
Y0
Y0
Cb0
Cr0
Cr0
Y1
Y1
Y1
Cr0