DSP56156FV40 MOTOROLA [Motorola, Inc], DSP56156FV40 Datasheet - Page 14

• Manufacturer Part Number: DSP56156FV40
• Description: 16-bit Digital Signal Processor
• Manufacturer: MOTOROLA [Motorola, Inc]

14
Pin Descriptions
On-Chip Codec
Power, Ground, and Clock
Power, Ground, and Clock
SPKM (Speaker Minus) — output. This pin is
SPKP (Speaker Plus) — output. This pin is
VREF (Voltage Reference) — output. This
V
VDIV (Voltage Division) — output. This
GND (Ground) — Ground pins
V
CCS
CC
the codec control register COCR. This
pin should be left floating when the co-
dec is not used.
the positive analog output from the on-
chip D/A converter. This pin should be
left floating when the codec is not used.
the negative analog output from the
on-chip D/A converter. This pin
should be left floating when the codec
is not used.
pin is the op-amp buffer output in the
reference voltage generator. It has a
value of (
ways be connected to the GNDA
through two capacitors, even when the
codec is not used.
output pin is also the output to the on-
chip op-amp buffer in the reference
voltage generator. It is connected to a
resistor divider network located within
the codec block which provides a volt-
age equal to (
be connected to the GND via a capacitor
when the codec is used and should be
left floating when the codec is not used.
(Power) — Power pins
(Synthesizer Power) — This pin sup-
plies a quiet power source to the Phase-
Locked Loop (PLL) to provide greater
frequency stability.
2
/
5
)V
2
/
CCA
5
)V
Freescale Semiconductor, Inc.
CCA
. This pin should al-
For More Information On This Product,
. This pin should
DSP56156 Data Sheet
Go to: www.freescale.com
EXTAL (External Clock) — input. This input
GNDA (Analog Ground) — This pin is the an-
GNDS (Synthesizer Ground) — This pin sup-
CLKO (Clock Output) — output. This pin
SXFC (External Filter Capacitor) — This pin
V
CCA
plies a quiet ground source to the PLL
to provide greater frequency stability.
(Analog Power) — This pin is the posi-
tive analog supply input. It should be con-
nected to V
alog ground return. It should be con-
nected to digital GND when the codec
is not used.
should be driven by an external clock or
by an external oscillator. After being
squared, the input frequency can be
used as the DSP core internal clock. In
that case, it is divided by two to produce
a four phase instruction cycle clock, the
minimum instruction time being two in-
put clock periods. This input frequency
is also used, after division, as input
clock for the on-chip codec and the on-
chip PLL.
outputs a buffered clock signal. By pro-
gramming two bits (CS1-CS0) inside
the PLL Control Register (PLCR), the
user can select between outputting a
squared version of the signal applied to
EXTAL, a squared version of the signal
applied to EXTAL divided by 2, and a
delayed version of the DSP core master
clock. The clock frequency on this pin
can be disabled by setting the Clockout
Disable bit (CD; bit 7) of the Operating
Mode Register (OMR). When disabled,
the pin can be left floating.
adds an external capacitor to the PLL
filter circuit. A low leakage capacitor
should be connected between and lo-
cated very close to SXFC and V
CC
when the codec is not used.
MOTOROLA
CCS
.