DSP56156FV40 MOTOROLA [Motorola, Inc], DSP56156FV40 Datasheet - Page 69

• Manufacturer Part Number: DSP56156FV40
• Description: 16-bit Digital Signal Processor
• Manufacturer: MOTOROLA [Motorola, Inc]

64
Design Considerations
DSP Programming Considerations
Bus Operation
Bus Operation
Figure 43 depicts the operation of the external memory interface with multiple wait states.
D0-D15
A0-A15
DSP Programming
Considerations
PS/DS
CLKO
R/W
WR
RD
BS
1. Synchronization of Status Bits
T0 T1
from Host to DSP
DMA, HF1, HF0, and HCP, HTDE,
and HRDF status bits are set or
cleared by the host processor side of
the interface. These bits are individ-
ually synchronized to the DSP clock.
(Refer to the DSP56156 User’s Manual,
I/O Interface section, Host/DMA In-
terface Programming Model for de-
scriptions of these status bits.)
Figure 43 Read and Write Bus Operation (3 Wait States)
T2 Tw T2
Freescale Semiconductor, Inc.
For More Information On This Product,
Tw
DSP56156 Data Sheet
T2 Tw
Go to: www.freescale.com
Data in
T2 T3
T0 T1 T2
2. Reading HF0 and HF1 as an
Encoded Pair
Care must be exercised when reading
status bits HF0 and HF1 as an encod-
ed pair, i.e., the four combinations 00,
01, 10, and 11 each have significance.
A very small probability exists that
the DSP will read the status bits syn-
chronized during transition. There-
fore, HF0 and HF1 should be read
twice and checked for consensus.
Tw T2 Tw
Data out
T2 Tw T2
T3 T0
MOTOROLA
T1
T