DSP56156FV40 MOTOROLA [Motorola, Inc], DSP56156FV40 Datasheet - Page 44

• Manufacturer Part Number: DSP56156FV40
• Description: 16-bit Digital Signal Processor
• Manufacturer: MOTOROLA [Motorola, Inc]

44
AC Electrical Characteristics and Timing
SSI Timing
Synchronous Serial Interfaces (SSI) Timing
(V
NOTE: All the timings for the SSI are given for a non-inverted serial clock polarity (SCKP=0 in CRB) and a non-
CC
FST (Transmit Frame Sync)
FSR (Receive Frame Sync) = SCx1 Pin
= 5.0 V dc ± 10%, T
inverted frame sync (FSI=0 in CRB). If the polarity of the clock and/or the frame sync have been inverted,
all the timings remain valid by inverting the clock signal SCK and/or the frame sync FSR/FST in the tables
and in the figures.
Num
130
131
132
133
134
135
136
137
138
139
Clock Cycle (See Note)
Clock High Period
Clock Low Period
Output Clock Rise/Fall Time
SCK Rising Edge to FSR Out
SCK Rising Edge to FSR Out
SCK Rising Edge to FSR Out
Data In Setup Time before SCK
Falling Edge
Data In Hold Time after SCK
Falling Edge
SCK Rising Edge to FSR Out
(bl) High
(bl) Low
(wl) High
(wl) Low
J
i ck a = Internal Clock, Asynchronous Mode (Asynchronous
Table 20 Synchronous Serial Interfaces Timing
i ck s = Internal Clock, Synchronous Mode (Synchronous implies
SCK = Serial Clock Pin
= -40 to + 125 C, C
Freescale Semiconductor, Inc.
x ck = External Clock
i ck = Internal Clock
wl = word length
bl = bit length
For More Information On This Product,
T = I
Characteristic
DSP56156 Data Sheet
= SCx0 Pin
implies that FSR and FST are two different frame syncs)
that only one frame sync FS is used)
CYC
Go to: www.freescale.com
/ 4
L
= 50 pF + 1 TTL Load)
40/50/60 MHz
Min
100
45
45
30
40
25
12
—
—
—
—
—
—
—
—
—
Max
32
18
32
15
32
15
32
15
—
—
—
—
—
—
—
7
Case
i ck a
i ck a
i ck a
i ck a
x ck
x ck
x ck
x ck
x ck
x ck
i ck
i ck
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MOTOROLA