DSP56156FV40 MOTOROLA [Motorola, Inc], DSP56156FV40 Datasheet - Page 23

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DSP56156FV40

Manufacturer Part Number
DSP56156FV40
Description
16-bit Digital Signal Processor
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
(V
MOTOROLA
Num
CC
21
22
23
24
25
28
29
= 5.0 V dc ± 10%, T
Delay from General-Purpose
Output Valid Caused by the
Execution of the First Inter-
rupt Instruction to IRQA,
IRQB Deassertion for Level
Sensitive Fast Interrupts — If
2nd Interrupt Instruction is:
(See Note 2)
Synchronous setup time from
IRQA, IRQB assertion to
Synchronous falling edge of
CLKO (See Notes 5 and 6)
Falling Edge of CLKO to First
Interrupt Vector Address Out
Valid after Synchronous
recovery from Wait State
(See Notes 3 and 5)
IRQA Width Assertion to
Recover from Stop State
(See Note 4)
Delay from IRQA Assertion to
Fetch of first instruction (exit-
ing Stop)
(See Notes 1 and 3)
Duration for Level Sensitive
IRQA Assertion to Cause the
Fetch of First IRQA Interrupt
Instruction (exiting Stop)
(See Notes 1 and 3)
Delay from Level Sensitive
IRQA Assertion to First Inter-
rupt Vector Address Out
Valid (exiting Stop)
(See Notes 1 and 3)
Table 13 Reset, Stop, Wait, Mode Select, and Interrupt Timing (continued)
Characteristics
Freescale Semiconductor, Inc.
OMR bit 6=0
OMR bit 6=1
OMR bit 6=0
OMR bit 6=1
OMR bit 6=0
OMR bit 6=1
Single Cycle
Two Cycles
For More Information On This Product,
J
= -40 to +125 C, C
Go to: www.freescale.com
524303T+4
524303T+4
524303T
27T+3
47T+4
47T+4
Min
DSP56156 Data Sheet
47T
14
15
40 MHz
L
= 50 pF + 1 TTL Load)
3 cyc - 29
cyc - 29
27T+20
Max
cyc-3
524303T+3
524303T+3
524303T
Reset, Stop, Wait, Mode Select, and Interrupt Timing
27T+3
47T+3
47T+3
Min
47T
13
13
50 MHz
AC Electrical Characteristics and Timing
3 cyc - 27
cyc - 27
27T+18
Max
cyc-2
524303T+3
524303T+3
524303T
27T+3
47T+3
47T+3
Min
47T
12
12
60 MHz
3 cyc - 26
cyc - 26
27T+16
Max
cyc-1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
23

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