DSP56156FV40 MOTOROLA [Motorola, Inc], DSP56156FV40 Datasheet - Page 27
DSP56156FV40
Manufacturer Part Number
DSP56156FV40
Description
16-bit Digital Signal Processor
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.DSP56156FV40.pdf
(76 pages)
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MOTOROLA
Num
30
31
32
33
DR Asserted to CLK high (Setup
Time for Synchronous Recovery
from Wait State)
CLK high to DSO (ACK) Valid
(Enter Debug Mode) after Syn-
chronous Recovery from Wait
State
DR to DSO (ACK) Valid
(Enter Debug Mode)
- After Asynchronous Recovery
- After Asynchronous Recovery
DR Assertion Width
- to Recover from Wait/Stop
- to Recover from Wait/Stop
- to Recover from Stop
(output)
Figure 15 Recovery from Wait State Using DR Pin — Synchronous Timing
from Stop State
from Wait State
without entering debug mode
short wake-up and enter
debug mode
long wake-up and enter
debug mode
(input)
DSO
DR
Characteristics
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Table 14 Wait and Stop Timings
DSP56156 Data Sheet
262157
18 cyc
29 cyc
18 cyc
29 cyc
Min
cyc
10
12
40 MHz
cyc - 4
10 cyc
Max
—
—
—
—
—
33
33
32
262157
18 cyc
29 cyc
18 cyc
29 cyc
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Min
cyc
11
9
50 MHz
AC Electrical Characteristics and Timing
cyc - 3
10 cyc
Max
—
—
—
—
—
262157
18 cyc
29 cyc
18 cyc
29 cyc
Min
cyc
10
8
60 MHz
cyc - 2
10 cyc
Max
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
27
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