DSP56156FV40 MOTOROLA [Motorola, Inc], DSP56156FV40 Datasheet - Page 7

• Manufacturer Part Number: DSP56156FV40
• Description: 16-bit Digital Signal Processor
• Manufacturer: MOTOROLA [Motorola, Inc]

Pin Descriptions
Address and Data Bus
A0-A15
D0-D15
Bus Control
MOTOROLA
PS/DS (Program/Data Memory Select) —
R/W (Read/Write) — three-state, active
(Address Bus) — three-state, active
high outputs. A0-A15 change in t0 and
specify the address for external pro-
gram and data memory accesses. If
there is no external bus activity, A0-A15
remain at their previous values. A0-A15
are three-stated during hardware reset.
(Data Bus) — three-state, active
high,
Read data is sampled on the trailing
edge of t2, while write data output is
enabled by the leading edge of t2 and
three-stated at the leading edge of t0. If
there is no external bus activity, D0-D15
are three-stated. D0-D15 are also three-
stated during hardware reset.
three-state, active low output. This out-
put is asserted only when external data
memory is referenced. PS/DS timing is
the same for the A0-A15 address lines.
PS/DS is high for program memory ac-
cess and is low for data memory access. If
the external bus is not used during an in-
struction cycle (t0, t1, t2, t3), PS/DS goes
high in t0. PS/DS is in the high imped-
ance state during hardware reset.
low output. Timing is the same as the
address lines, providing an “early
write” signal. R/W (which changes in
t0) is high for a read access and is low
for a write access. If the external bus is
not used during an instruction cycle
bidirectional
Freescale Semiconductor, Inc.
For More Information On This Product,
input/outputs.
Go to: www.freescale.com
DSP56156 Data Sheet
WR (Write Enable) — three-state, active
RD (Read Enable) — three-state, active
BS (Bus Strobe) — three-state, active
(t0, t1, t2, t3), R/W goes high in t0. R/W
is three-stated during hardware reset.
low output. This output is asserted dur-
ing external memory write cycles. When
WR is asserted in t1, the data bus pins
D0-D15 become outputs and the DSP
puts data on the bus during the leading
edge of t2. When WR is deasserted in t3,
the external data has been latched inside
the external device. When WR is assert-
ed, it qualifies the A0-A15 and PS/DS
pins. WR can be connected directly to
the WE pin of a static RAM. WR is three-
stated during hardware reset or when
the DSP is not bus master.
low output. This output is asserted
during external memory read cycles.
When RD is asserted in late t0/early t1,
the data bus pins D0-D15 become in-
puts and an external device is enabled
onto the data bus. When RD is deas-
serted in t3, the external data is latched
inside the DSP. When RD is asserted, it
qualifies the A0-A15 and PS/DS pins.
RD can be connected directly to the
OE pin of a static RAM or ROM. RD is
three-stated during hardware reset or
when the DSP is not bus master.
low output. Asserted at the start of a
bus cycle (during t0) and deasserted at
the end of the bus cycle (during t2).
This pin provides an “early bus start”
signal which can be used as address
latch and as an “early bus end” signal
which can be used by an external bus
controller. BS is three-stated during
hardware reset.
Address and Data Bus
Pin Descriptions
Bus Control
7