MK68564N-04 STMICROELECTRONICS [STMicroelectronics], MK68564N-04 Datasheet - Page 10

• Manufacturer Part Number: MK68564N-04
• Description: SERIAL INPUT OUTPUT
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

DATA PATH
The transmit and receive data paths for each chan-
nel are shown in figure 6. The receiver has three
8-bit buffer registers in a FIFO arrangement (to pro-
vide a 3-byte delay) in addition to the 8-bit receive
shift register. This arrangement creates additional
time for the CPU to service an interrupt at the begin-
ning of a block of high-speed data. The receiver er-
ror FIFO stores parity and framing errors and other
types of status information for each of the three
bytes in the receive data FIFO. The receive error FI-
FO is loaded at the same time as the receive data
FIFO. The contents of the receive error are read
through the upper four bits in Status Register 1.
Incoming data is routed through one of several
paths, depending on the mode and character length.
In the Asynchronous modes, serial data is entered
into the 3-bit buffer, if it has a character length of se-
ven or eight bits, or the data is entered into the 8-bit
receive shift register, if it has a length of five or six
bits.
In the Synchronous mode, the data path is determi-
ned by the phase of the receive process currently in
operation. A Synchronous Receive operation be-
gins with the receiver in the Hunt phase, during
which time the receiver searches the incoming data
stream for a bit pattern that matches the prepro-
grammed sync characters (or flags in the SDLC
mode). If the device is programmed for Monosync
Hunt, a match is made with a single sync character
stored in Sync Word Register 2. In Bisync Hunt, a
match is made with the dual sync characters stored
in Sync Word Registers 1 and 2. In either case, the
incoming data passes through the receive sync re-
gister and is compared against the programmed
sync characters in Sync Word Registers 1 and 2.
In the Monosync mode, a match between the sync
character programmed into Sync Word Register 2
and the character assembled in the receive sync re-
gister establishes synchronization.
In the Bysync mode, incoming data is shifted to the
receive shift register, while the next eight bits of the
message are assembled in the receive sync regis-
ter. The match between the assembled character in
the sync register and the programmed character in
Sync Word Register 2, and between the character
in the shift register and the programmed character
in Sync Word Register 1 establishes synchroniza-
tion. Once synchronization is established, incoming
data bypasses the receive sync register and directly
enters the 3-bit buffer.
In the SDLC mode, all incoming data passes
through the receive sync register, which continuous-
ly monitors the receive data stream and performs
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zero deletion when indicated. Upon receiving five
contiguous ones, the sixth bit is inspected. If the
sixth bit is a 0, it is deleted from the data stream. If
the sixth bit is a 1, the seventh bit is inspected. If the
seventh bit is a 0, a Flag sequence has been recei-
ved ; if the seventh bit is a 1, an Abort sequence has
been received.
The reformatted data from the receive sync register
enters the 3-bit buffer and is transferred to the re-
ceive shift register. Note that the SDLC receive ope-
ration also begins in the Hunt Phase, during which
time the SIO tries to match the assembled character
in the receive sync register with the flag pattern in
Sync Word Register 2. Once the first flag character
is recognized, all subsequent data is routed through
the path described above, regardless of character
length.
Although the same CRC checker is used for both
SDLC and synchronous data, the path taken for
each mode is different. In Bisync protocol, the byte-
oriented operation requires that the CPU decide
whether or not to include the data character in the
CRC calculation. To allow the CPU ample time to
make this decision, the SIO provides an 8-bit delay
before the data enters the CRC checker. In the
SDLC mode, no delay is provided, since CRC is cal-
culated on all data between the opening and closing
flags.
The transmitter has an 8-bit transmit data register,
which is loaded from the internal bus, and a 20-bit
transmit shift register, which can be loaded from
Sync Word Register 1, Sync Word Register 2, and
the transmit data register. Sync Word Registers 1
and 2 contain sync characters in the Monosync, Bi-
sync, or External Sync modes, or address field (one
character long) and flag, respectively, in the SDLC
mode. During Synchronous modes, information
contained in Sync Word Registers 1 and 2 is loaded
into the transmit shift register at the beginning of the
message and, as a time filler, in the middle of the
message if a Transmit Underrun condition occurs.
In SDLC mode, the flags are loaded into the transmit
shift register at the beginni n g and end of the mes-
sage.
Asynchronous data in the transmit shift register is
formatted with start and stop bits, and it is shifted out
to the transmit multiplexer at the selected clock rate.
Synchronous (Monosync, Bisync, or External Sync)
data is shifted out to the transmit multiplexer and al-
so the CRC generator at the x1 clock rate.
SDLC/HDLC data is shifted out through the zero in-
sertion logic, which is disabled while flags are being
sent. For all other fields (address, control, and frame
check), a 0 is inserted following five contiguous ones