MK68564N-04 STMICROELECTRONICS [STMicroelectronics], MK68564N-04 Datasheet - Page 27

• Manufacturer Part Number: MK68564N-04
• Description: SERIAL INPUT OUTPUT
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

D5, D4, D3 : Command Codes
Command 0 (Null). The Null command has no ef-
fect on the MK68564 SIO.
Command 1 (Send Abort). This command is used
in SDLC mode to transmit a sequence of eight to
thirteen ones. This command always empties the
transmit buffer ans sets the Tx Underrun/EOM Latch
in Status Register 0 to a one
Command 2 (Reset External/Status Interrupts). Af-
ter an External/Status interrupt (a change on a mo-
dem line or a Break condition, for example), the up-
per five bits in Status Register 0 are latched. This
command reenables these bits and allows interrupts
to occur again as a result of a status change. Lat-
ching the status bits captures short pulses, until the
CPU has time to read the change. This command
should be issued prior to enabling External/Status
Interrupts.
Command 3 (Channel Reset). This command di-
sables both the receiver and transmitter, forces TxD
to a marking state (”1”), forces the modem control
signals high, resets any pending interrupts from this
channel, and resets all control registers. See the Re-
set section in the SIO System Interface Description
for a more detailed list. All control registers for the
channel must be rewritten after a Channel Reset
command.
Command 4 (Enable Interrupt On Next Rx Charac-
ter). This command is used to reactivate the Receive
Interrupt On First Character Only interrupt mode.
This command is normally issued after the present
message is completed but before the next message
has started to be assembled. The next character to
enter the receive data FIFO after this command is
issued will cause a receiver interrupt request.
Note : If the data FIFO has more than one character
stored when this command is issued, the first pre-
viously stored character will cause the receiver in-
terrupt request.
Command CMD2 CMD1 CMD0
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Null Command
(no effect)
Send Abort
(SDLC mode)
Reset External/
Status Interrupts
Channel Reset
Enable Interrupt On
Next Rx Character
Reset Tx Interrupt
Pending
Error Reset
Null Command
(no effect)
Command 5 (Reset Tx Interrupt Pending). When
the Transmit Interrupt Enable mode is selected, the
transmitter requests an interrupt when the transmit
buffer becomes empty. In those cases, where there
are no more characters to be sent (at the end of
message, for example), issuing this command re-
sets the pending transmit interrupt and prevents any
further transmitter interrupt requests until the next
character has been loaded into the transmit buffer
or until CRC has been completely sent.
Command 6 (Error Reset). This command resets
the upper seven bits in Status Register 1. Anytime
a Special Receive Condition exists when Receive
Interrupt On First Character Only mode is selected,
the data with the special condition is held in the re-
ceive data FIFO until this command is issued.
Command 7 (Null). The Null command has no ef-
fect on the MK68564 SIO.
D2, D1 : Not Used (read as zeros)
D0 : Loop Mode
When this bit is set to a 1, the transmitter output is
connected to the receiver input and TxC is connec-
ted to the receiver clock. RxC and RxD pins are not
used by the receiver ; they are bypassed internally.
RxC may still be used as the baud rate generator
output in Loop Mode.
MODE CONTROL REGISTER (MODECTL)
The Mode Control Register contains control bits that
affect both the receiver and the transmitter. This re-
gister must be initialized before loading the Interrupt,
Tx, and Rx Control Registers, and the Sync Word
Registers. This register is reset to ”00H” by a chan-
nel or hardware reset.
D7, D6 : Clock Rate 1 and 0
These bits specify the multiplier between the input
shift clock rates (TxC x RxC) and data rate. The
same multiplier is used for both the transmitter and
receiver, although the input clock rates may be dif-
ferent. In x16, x32, and x64 clock modes, the recei-
ver start bit detection logic is enabled ; therefore, for
Synchronous modes, the x1 clock rate must be
specified. Any clock rate may be specified for Asyn-
chronous mode ; however, if the x1 clock rate is se-
lected, synchronization between the receive data
and the receive clock must be accomplished exter-
nally.
CLOCK
RATE
D7
1
CLOCK
RATE
D 6
0
MODE
SYNC
D5
1
MODE
SYNC
D 4
0
STOP
BITS
D3
1
BITS 0
STOP
D2
PARITY
E/O
D 1
PARITY
ON/OFF
D0
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