MK68564N-04 STMICROELECTRONICS [STMicroelectronics], MK68564N-04 Datasheet - Page 30

• Manufacturer Part Number: MK68564N-04
• Description: SERIAL INPUT OUTPUT
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

terminated, or at the beginning of CRC transmission
when the Transmit Underrun/EOM latch in Status
Register 0 becomes set. When this bit is zero, no Ex-
ternal/Status interrupts will occur.
If this bit is set when an External/Status condition is
pending, an interrupt will be requested. It is re-
commended that a Reset External/Status Interrupts
command (Command 2 in the Command Register)
be issued prior to enabling External/Status inter-
rupts.
SYNC WORD REGISTER 1 (SYNC 1)
This register is programmed to contain the transmit
sync character in the Monosync mode, the first eight
bits of the 16-bit sync character in the Bysinc mode,
or the transmit sync character in the External Sync
mode. This register is not used in Asynchronous
mode. In the SDLC mode, this register is program-
med to contain the secondary address field used to
compare against the address field of the SDLC
frame. The SIO does not automatically transmit the
station address at the beginning of a response
frame. This register is reset to ”00H” by a channel
or hardware reset.
SYNC WORD REGISTER 2 (SYNC 2)
This register is programmed to contain the receive
sync character in the Monosync mode, the last eight
bits of the 16-bit sync character in the Bisync mode,
or a flag character (01111110) in the SDLC mode.
This register is not used in the External Sync mode
and the Asynchronous mode. This register is reset
to ”00H” by a channel or hardware reset.
RECEIVER CONTROL REGISTER
(RCVCTL)
This register contains the control bits and parame-
ters for the receiver logic. This register is reset to
”00H” by a channel or hardware reset.
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RX BITS
SYNC/
SYNC/
CHAR 1
SDLC7
SDLC
D7
D7
D 7
15
SDLC6
RX BITS
SYNC/
SYNC/
CHAR 0
SDLC
D 6
D 6
D 6
14
SDLC5
RX AUT O
SYNC/
SYNC/
SDLC
ENAB.
D5
D5
13
D 5
SDLC4
SYNC/
SYNC/
SDLC
D 4
D 4
MO DE
H UNT
12
D 4
SDLC3
SYNC/
SYNC/
SDLC
RX CRC
D3
D3
11
ENAB.
D 3
SDLC2
SYNC/
SYNC/
SDLC
SEARCH
D 2
D2
10
ADDR.
D 2
SYNC/
SDLC1
SDLC
SYNC/
D1
D1
STRIP
SYNC
9
D 1
SDLC 8
SDLC0
SYNC/
ENABLE
SYNC/
D0
D0
D 0
RX
D7, D6 : Receiver Bits/Character 1 and 0
The state of these two bits determines the number
of bits to be assembled as a character in the recei-
ved serial data stream. If Parity is enabled, one ad-
ditional bit will be added to each character. The num-
ber of bits per character can be changed while a
character is being assembled but only before the
number of bits currently programmed is reached. All
data is right-justified in the shift register and trans-
ferred to the receive data FIFO in 8-bit groups.
In Asynchronous mode, transfers are made at char-
acter boundaries, and all unused bits of character
are set to a one. In Synchronous modes and SDLC
mode, an 8-bit segment of the serial data stream is
transferred to the data FIFO when the internal coun-
ter reaches the number of bits per character pro-
grammed. For less than eight bits per character, no
parity, the MSB bit(s) of the first transfer will be the
LSB bit(s) of the next transfer.
D5 : Receiver Auto Enables
When this bit is set to a one, and the Receiver Ena-
ble bit is also set, a Low on the DCD input pin be-
comes the enable for the receiver. When this bit is
zero, the DCD pin is simply an input to the SIO, and
its status is displayed in Status Register 0.
D4 : Enter Hunt Mode
This bit, when written to a one, rearms the receiver
synchronization logic and forces the comparison of
the received bit stream to the ontents of Sync Word
Register 1 and/or Sync Word Register 2, depending
upon which Synchronous mode is selected, until bit
synchronization is achieved. The SIO automatically
enters the Hunt mode after a channel or hardware
reset, after an Abort condition is detected, or when
the receiver is disabled. When the Hunt mode is en-
tered, the Hunt/Sync bit in Status Register 0 is set
to a one. When synchronization is achieved, the
Hunt/Sync bit is reset to a zero. If External/Status in-
terrupts are enabled, an interrupt request will be ge-
nerated on both transitions of the Hunt/Sync bit. En-
ter Hunt Mode has no affect in Asynchronous
modes. This bit is not latched and will always be read
as a zero.
R X BITS
CHAR 1
0
0
1
1
RX BITS
CHAR 0
0
1
0
1
Bits/character
(no parity)
5
6
7
8
Bits/character
(parity)
6
7
8
9