MK68564N-04 STMICROELECTRONICS [STMicroelectronics], MK68564N-04 Datasheet - Page 25

• Manufacturer Part Number: MK68564N-04
• Description: SERIAL INPUT OUTPUT
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Receiver Characteristics. The receiver may be
programmed to assemble five to eight data bits into
a character. The character is right-justified in the
shift register and transferred to the receive data FI-
FO. All data transfers to the FIFO are in 8-bit groups.
When the character length programmed is less than
eight bits, the most significant bit(s) transferred with
a character, will be the least-significant bit(s) of the
next character. The character length programmed
may be changed on the fly during the reception of a
frame ; however, care must be taken to assure that
the change is effective, before the number of bits
specified for the character length has been assem-
bled.
The address field in the SDLC frame is defined as
an 8-bit field. When the Address Search Mode is se-
lected, the receiver will compare the 8-bit character
following the flag (first non-flag character) against
the address programmed in Sync Word Register 1
or the hardwired global address (11111111). When
the address field of the SDLC frame matches either
address, data transfer will begin with the address
character being loaded into the receive data FIFO.
If the frame address does not match either address,
the receiver will remain idle and continue checking
every frame received for an address match. The ad-
dress comparison is always done on the first eight
bits following a flag, regardless of the bits per char-
acter programmed.
The SIO receiver is capable of matching only one
address character. Once a match occurs, all data is
transferred to the receive data FIFO at the program-
med bits per character rate. If SDLC extended ad-
dress field recognition is used (two or more address
characters), the CPU program must be capable of
determining whether or not the frame has a correct
address field. If the correct address field is not recei-
ved, the Hunt bit can be set to suspend reception
and start searching for the next frame. The control
field of an SDLC frame is transparent to the SIO ; it
is transferred to the data FIFO as a data character.
All extra zeros, inserted in the data stream by the
transmitter, are automatically deleted in the recei-
ver.
Data Transfer and Status Monitoring. After re-
ceipt of a valid flag, the assembled characters are
transferred to the receive data FIFO, and the status
information for each character is transferred to the
receive error FIFO. The following four modes are
available to transfer the received data and its asso-
ciated status to the CPU.
No Receiver Interrupts Enabled. This mode is u-
sed for polling operations or for off-line conditions.
When transferring data, using a polling routine, the
Rx Character Available bit in Status Register 0
should be checked to determine whether or not a re-
ceive character is available for transfer. Only when
a character is available should the receive buffer
and Status Register 1 be read. The Rx Character
Available bit is set to a one every time a character
is shifted to the top of the receive data FIFO. This
bit is reset when the receive buffer is read.
Interrupt On First Character Only. This interrupt
mode is normally used to start a DMA transfer rou-
tine, or in some cases, a polling loop. The SIO will
generate an interrupt the first time a character is shif-
ted to the top of the receive data FIFO after this
mode is selected or reinitialized. An interrupt will be
generated thereafter only if a Special Receive
Condition is detected. This mode is reinitialized with
the Enable Interrupt On Next Received Character
command. Parity Errors do not cause interrupts in
this mode, but a Receive Overrun Error or an End
Of Frame condition will.
Interrupt On Every Character. This interrupt mode
will generate a Receiver Interrupt every time a char-
acter is shifted to the top of the receive data FIFO.
A Special Receive Condition interrupt on a Parity er-
ror is optional in this mode.
Special Receive Condition Interrupt. The special
condition interrupt mode is not an interrupt mode, as
such, but works in conjunction with Interrupt On E-
very Character or Interrupt On First Character Only
modes. When the Status Affects Vector bit in either
channel is set, a Special Receive Condition will mo-
dify the Receive Interrupt vector to signal the CPU
of the special condition. Receive Overrun Error, Pa-
rity Error, and End Of Frame are the Special Receive
Conditions in SDLC mode. The Overrun and Parity
error status bits in Status Register 1 are latched
when they occur ; the End Of Frame bit is not lat-
ched. The two bits that are latched will remain lat-
ched and will generate a Special Receive Condition
Interrupt at every character available time until an
Error Reset command is issued. Since the two sta-
tus bits are latched, the error status in Status Regis-
ter 1, when read, will reflect an error in the current
word in the receive buffer, in addition to any Parity
or Overrun errors received since the lastError Reset
command.
SDLC Receive CRC Checking. Control of the re-
ceiver CRC checker is automatic. It is reset by the
leading flag, and CRC is calculated up to the final
flag. The byte that has the End Of Frame bit set is
the byte that contains the result of the CRC check.
If the CRC/Framing Error bit is not set (zero), the
CRC indicates a valid received message. A special
check sequence is used for the SDLC check, be-
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