MK68564N-04 STMICROELECTRONICS [STMicroelectronics], MK68564N-04 Datasheet - Page 4

• Manufacturer Part Number: MK68564N-04
• Description: SERIAL INPUT OUTPUT
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SIO SYSTEM INTERFACE
INTRODUCTION
The MK68564 SIO is designed for simple and effi-
cient interface to a MK68000 CPU system. All data
transfers between the SIO and the CPU are asyn-
chronous to the system clock. The SIO system
timing is derived from the chip select input (CS) du-
ring normal read and write sequences, and from the
interrupt acknowledge input (IACK) during an ex-
ception processing sequence. CS is a function of
address decode and (normally) lower data strobe
(LDS). IACK is a function of the interrupt level on ad-
dress lines A1, A2, and A3, an interrupt acknow-
ledge function code (FC0-FC2), and LDS.
Note : CS and IACK can never be asserted at the
same time.
Note : Unused inputs should be pulled up or down,
but never left floating.
READ SEQUENCE
The SIO will begin a read cycle if, on the falling edge
of CS, the read-write (R/W) pin is high. The SIO will
respond by decoding the address bus (A1-A5) for
the register selected, by placing the contents of that
register on the data bus pins (D0-D7), and by driving
the data transfer acknowledge (DTACK) pin low. If
the register selected is not implemented on the SIO,
the data bus pins will be driven high, and then
DTACK will be asserted. When the CPU has acqui-
red the data, the CS signal is driven high, at which
time the SIO will drive DTACK high and then three-
state DTACK and D0-D7.
WRITE SEQUENCE
The SIO will begin a write cycle if, on the falling edge
of CS, the R/W pin is low. The SIO will respond by
latching the data bus, by decoding the address bus
for the register selected, by loading the register with
the contents of the data bus, and by driving DTACK
low. When the CPU has finished the cycle, the CS
input is driven high. At this time, the SIO will drive
DTACK high and will then three-state DTACK. If the
register selected is not implemented on the SIO, the
normal write sequence will proceed, but the data
bus contents will not be stored.
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INTERRUPT SEQUENCE
The SIO is designed to operate as an independent,
interrupting peripheral, or, when interconnected
with other components, an interrupt priority daisy
chain can be formed.
Independent Operation. Independent operation
requires that the interrupt enable in pin (IEI) be
connected to ground. The SIO starts the interrupt
sequence by driving the interrupt request pin (INTR)
low. The CPU responds to the interrupt by starting
an interrupt acknowledge cycle, in which the SIO
IACK pin is driven low. The highest priority interrupt
request in the SIO,at the time IACK goes low, places
its vector on the data bus pins. The SIO releases the
INTR pin and drives DTACK low. When the CPU has
acquired the vector, the IACK signal is driven high.
The SIO responds by driving DTACK to a high level
and then three-stating DTACK and D0-D7. If more
than one interrupt request is pending at the start of
an interrupt acknowledge sequence, the SIO will
drive the INTR pin low following the completion of
the interrupt acknowledge cycle. This sequence will
continue until all pending interrupts are cleared. If
the SIO is not requesting an interrupt when IACK
goes low, the SIO will not respond to the IACK signal
; DTACK and the data bus will remain three-stated.
Daisy Chain Operation. The interrupt priority chain
is formed by connecting the interrupt enable out pin
(IEO) of a higher priority part to IEI of the next lower
priority part. The highest priority part in the chain
should have IEI tied to ground. The Daisy Chaining
capability (figures 2 and 3) requires that all parts in
a chain have a common IACK signal. When the
common IACK goes low, all parts freeze and priori-
tize interrupts in parallel . Then priority is passed
down the chain, via IEI and IEO, until a part which
has a pending interrupt, once IEI goes low, passes
a vector, does not propagate IEO, and generates
DTACK.
The state of the IEI pin does not affect the SIO in-
terrupt control logic. The SIO can generate an inter-
rupt request any time its interrupts are enabled. The
IEO pin is normally high ; it will only go low during
an IACK cycle if IEI is low and no interrupt is pending
in the SIO. The IEO pin will be forced high whenever
IACK or IEI goes high.