MK68564N-04 STMICROELECTRONICS [STMicroelectronics], MK68564N-04 Datasheet - Page 26

• Manufacturer Part Number: MK68564N-04
• Description: SERIAL INPUT OUTPUT
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

cause the transmitted CRC character is inverted.
The final check must be 0001110100001111. he 2-
byte CRC check characters should be read and dis-
carded by the CPU, because the last two bits of the
2-byte SDLC CRC check characters are not trans-
ferred to the receive data FIFO due to the internal
timing associated with detecting the closing flag.
Unlike Synchronous modes, the logic path in SDLC
mode does not have an 8-bit delay between the time
a character is transferred to the receive data FIFO
and the time a character enters the CRC checker.
This delay is not needed, because in SDLC, all char-
acters between the opening and closing flags are in-
cluded in the CRC calculations. When the second
CRC character (six bits only) is loaded into the re-
ceive buffer, CRC calculation is complete.
SDLC Receive Termination. An SDLC frame is ter-
minated when the closing flag is detected. The de-
tection of the flag sets the End Of Frame bit in Status
Register 1 and generates a Special Receive Condi-
tion Interrupt. In addition to the End Of Frame bit
being set and the results of the CRC check, Status
Register 1 has three bits of Residue code valid at
this time. The Residue bits indicate the boundary
between the CRC check bits and the I-field bits in the
frame. A detailed description of the Residue code
bits is given in the Register Description section, un-
der Status Register 1.
Any frame can be prematurely aborted by an Abort
sequence. Aborts are detected if seven or more
continuous ones occur in the received data stream.
This condition will cause an External/Status Inter-
rupt to be generated with the Break/Abort bit in Sta-
tus Register 0 set. After the Reset External/Status
Interrupts command has been issued, a second in-
terrupt will occur when the continuous ones condi-
tion has been cleared. This second interrupt can be
used to distinguish between the Abort and Idle line
conditions.
REGISTER DESCRIPTION
The following sections describe the MK68564 SIO
registers. Each register is detailed in terms of bit
configuration, the active states of each bit, their de-
finitions, their functions, and their effects upon the
internal hardware and external pins.
COMMAND REGISTER (CMDREG)
This register contains command and reset functions
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used in the programming of the SIO. This register is
reset to ”00H” by a channel or hardware reset. All
bits, except Loop Mode, will be read as zeros during
a read cycle.
D7, D6 : Reset Codes 1 and 0
Null Code. The null code has no effect on the
MK68564 SIO. It is used when writing to the
Command Register for some reason other than a
CRC Reset.
Reset Receiver CRC Checker. It is necessary in
Synchronous modes (except SDLC) to reset the re-
ceiver CRC circuitry between received messages.
The CRC circuitry may be reset by one of the follo-
wing : disabling the receiver, setting the Enter Hunt
Mode bit in the Receiver Control Register, or issuing
this Reset command. The CRC circuitry is reset
automatically in SDLC mode when the End Of
Frame flag is detected. This Reset command will ini-
tialize the CRC checker circuit to all ones in SDLC
mode and all zeros in the other Synchronous
modes.
Reset Transmit CRC Generator. This command
resets the CRC generator to all ones in SDLC mode
and all zeros in the other Synchronous modes. This
command should be issued after the transmitter is
enabled but before the first character of a message
is loaded in the transmit buffer.
Reset Transmit Underrun/EOM Latch. This
command resets the Underrun/EOM latch in Status
Register 0 if the transmitter is enabled. The Under-
run/EOM latch controls the transmission of CRC at
the end of a message in Synchronous modes. When
a transmit underrun occurs and this latch is low,
CRC will be appended to the end of the transmis-
sion.
CRC
CRC 1
D7
1
0
0
1
1
CRC
D6
0
CRC 0
CMD
0
1
0
1
D5
2
Null Code (no effect)
Reset Receiver CRC Checker
Reset Transmit CRC Generator
Reset Tx Underrun/End of
Message Latch
CMD
D4
1
CMD
D3
0
D2
D1
MODE
LOOP
D0