MK68564N-04 STMICROELECTRONICS [STMicroelectronics], MK68564N-04 Datasheet - Page 24

• Manufacturer Part Number: MK68564N-04
• Description: SERIAL INPUT OUTPUT
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

more bits to send. It does this by first sending the two
bytes of CRC and the following these with one or
more flags. This technique allows very high-speed
transmission under DMA or CPU control, without re-
quiring the CPU to respond quickly to the end of
message situation.
The action that the SIO takes in the underrun situa-
tion depends on the state of the Transmit Under-
run/EOM status bit in status Register 0. Following a
reset, the Transmit Underrun/EOM bit is set to a one
and prevents the insertion of CRC characters during
the time there is no data to send. Consequently, flag
characters are sent. If the Transmit Underrun/EOM
status bit is zero when the underrun condition oc-
curs, the 16-bit CRC character is sent, followed by
one or more flag characters. The Transmit Under-
run/EOM bit is reset to zero by issuing the Reset Tx
Underrun/EOM Latch command in the Command
Register.
The SIO begins to send a frame when data is written
into the transmit buffer. Between the time the first
data byte is written and the end of the message, the
Reset Tx Underrun/EOM Latch command must be
issued. The Transmit Underrun/EOM status bit will
then be in the reset state at the end of the message
(when underrun occurs), and CRC characters will
automatically be sent. The transmission of the first
CRC bit set the Transmit Underrun/EOM status bit
to a one and generates an External/Status interrupt.
Also, while CRC is being sent, the Tx Buffer Empty
bit in Status Register 0 is reset to indicate that the
transmit shift register is full of CRC data. When CRC
has been completely sent, the Tx Buffer Empty sta-
tus bit is set, and a Transmit Interrupt is generated
to indicate that another message may begin. This in-
terrupt occurs because CRC has been sent, and a
flag has been loaded into the shift register. If no
more messages are to be sent, the program can ter-
minate transmission by disabling the transmitter.
Although there is no restriction as to when the Trans-
mit Underrun/EOM bit can be reset within a mes-
sage, it is usually reset after the first data character
(secondary address field) is sent to the SIO. By re-
setting the status bit early in the message, the CPU
has additional time (16 bits of CRC) to recognize if
an unintentional transmit underrun situation has oc-
cured and to respond with an Abort command. Is-
suing the Abort command stops the flags from going
on the line prematurely and eliminates the possibility
of the receiver accepting the frame as valid data.
This situation can happen if, at the receiving end, the
data pattern immediately preceding the automatic
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flag insertion matches the CRC checker, giving a
false CRC check result.
CRC Generation. The CRC generator must be re-
set to all ones at the beginning of each frame before
CRC accumulation can begin. Actual accumulation
begins on the first data character (address field) loa-
ded into the transmit buffer. The Tx CRC Enable bit
in the Transmit Control Register should be set to a
one before the first character is loaded into the trans-
mit buffer. In SDLC mode, all characters between
the opening and the closing flags are included in
CRC accumulation. The output of te CRC generator
is inverted before it is transmitted.
Transmit Termination. The normal sequence at
the end of a frame is
A Transmit Interrupt occurs when the last data char-
acter written to the transmit buffer is downloaded in-
to the transmit shift register. This interrupt may be
cleared by issuing a Reset Tx Interrupt Pending
command.
An External/Status Interrupt occurs when the first bit
of the CRC character is transmitted. This interrupt
condition should first be tested to see if the interrupt
was caused by the Tx Underrun/EOM bit going High
and then reset by issuing a Reset External/Status In-
terrupts command.
A Transmit Interrupt occurs when the first bit of the
flag is transmitted. This interrupt may be cleared by
issuing a Reset Tx Interrupt Pending command, by
loading the first character of the next message, or
by disabling the transmitter.
If the transmitter is disabled while a character is
being sent, that character (data or flag) is sent in the
normal fashion but is followed by a marking line ra-
ther than CRC or more flag characters. If CRC char-
acters are being sent at the time the transmitter is
disabled, all 16 bits will be transmitted, followed by
a marking line ; however, flags are sent in place of
CRC. A character in the buffer when the transmitter
is disabled remains in the buffer.
SDLC RECEIVE
Initialization. The receiver is enabled only after all
of the receive parameters are initialized. After the
Receiver Enable bit in the Receiver Control Register
is set to a one, the receiver will be in the Hunt phase
and will remain in this phase until the first flag is re-
ceived. While in the SDLC mode, the receiver never
re-enters the Hunt phase, unless specifically in-
structed to do so by the program or when an Abort
character is detected in the incoming data stream.