MK68564N-04 STMICROELECTRONICS [STMicroelectronics], MK68564N-04 Datasheet - Page 20

• Manufacturer Part Number: MK68564N-04
• Description: SERIAL INPUT OUTPUT
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Bisync Protocol Transmission. In a Bisync Proto-
col operation, once synchronization is achieved be-
tween the transmitter and receiver, fill characters
are inserted to maintain that synchronization when
the transmitter has no more data to send. The diffe-
rent options available in the SIO are described in the
Transmit Underrun/End Of Message part of this sec-
tion. If pad characters are to be sent in place of sync
characters following the transmission of the CRC,
the program can set the SIO transmitter to eight bits
per character and then load ”FFH” to the transmit
buffer while the CRC characters are being sent. Al-
ternatively, the sync characters in Sync Word Regis-
ters 1 and 2 can be redefined to be pad characters
during this time. The following example is included
to clarify this point :
The SIO interrupts the CPUwith a Transmit Interrupt
when the Tx Buffer Empty bit is set.
The CPU recognizes that the last character (ETX) of
the message has already been sent to the SIO
transmit buffer by examining the internal program
status.
To force the SIO to send CRC, the CPU issues the
Reset Tx Underrun/EOM Latch command and
clears the current Transmit Interrupt with the Reset
Tx Interrupt Pending command. Resetting the inter-
rupt with this command prevents the SIO from re-
questing more data. The SIO then begins to send
CRC (because the transmitter is in an underrun
condition) and sets the Transmit Underrun/EOM
Latch, which causes an External/Status Interrupt.
The CPU satisfies the External/Status Interrupt by
loading pad characters into the transmit buffer and
clears the interrupt by issuing the Reset Exter-
nal/Status Interrupt command.
The pad character will follow the CRC characters in
this sequence, instead of the usual sync characters.
A Transmit Interrupt is generated when the pad
character is loaded into the transmit shift register.
From this point on, the CPU can send more pad
characters or sync characters.
The transparent mode of operation in Bisync Proto-
col is made possible with the SIO’s ability to change
the Tx CRC Enable bit at any time during program
sequencing and with the additional capability of in-
serting 16-bit sync characters. Exclusion of DLE
(Data Link Escape) characters from CRC calcula-
tion can be achieved by disabling CRC calculations
immediately preceding the DLE character transfer
to the transmit buffer. In the case of a transmit un-
derrun condition in the transparent mode, a pair of
DLE-SYN characters is sent. The SIO can be pro-
grammed to send the DLE-SYNC sequence by loa-
20/46
ding a DLE character into Sync Word Register 1 and
a SYNC character into Sync Word Register 2.
The SIO always transmits two sync characters (16
bits) in Bisync mode. If additional sync characters
are to be transmitted before a message, the CPU
can delay loading data to the transmit buffer until the
required number of syncs have been sent. No CRC
calculations are done on any automatically inserted
sync characters. An alternate method of sending
additional sync characters is to load the sync char-
acters into the transmit buffer, in which case the
transmitter will treat the characters as data. The Tx
CRC Enable bit should not be set, until true data is
going to be loaded into the buffer, to avoid perfor-
ming CRC calculations on the additional sync char-
acters.
SYNCHRONOUS RECEIVE
Initialization. Byte-oriented receive programs are
usually initialized with the following parameters :
odd-even or no parity, x1 clock mode (necessary be-
cause of the start bit detection logic), 8- or 16-bit
sync character(s), CRC polynomial, Receiver En-
ables, interrupt modes, and receive character
length. Care must be taken if Parity is enabled. The
receiver will usually detect a Parity Error on all sync
characters, after synchronization is achieved, and
on the CRC characters.
Receiver Hunt Mode. After the SIO is initialized for
a Synchronous receive operation, the receiver is in
the Hunt phase. During the Hunt phase, the receiver
does a bit-by-bit comparison of the incoming data
stream and the sync character(s) stored in the Sync
Word Register 2 (for Monosync mode) and Sync
Word Registers 1 and 2 (for Bisync mode). When a
match occurs, the Hunt phase is terminated, and the
following data bits are assembled into the program-
med character length and loaded into the receive
data FIFO.
Receive Characteristics. The receiver may be pro-
grammed to assemble five to eight data bits into a
character. The character is right-justified in the shift
register and transferred to the receive data FIFO. All
data transfers to the FIFO are in 8-bit groups. When
the programmed character length is less than eight
bits, the most significant bit(s) transferred with a
character will be the least significant bit(s) of the next
character. The programmed character length may
be changed on the fly during a message ; however,
care must be taken to assure that the change is ef-
fective before the number of bits specified for the
character length have been assembled.
When the Sync Character Load Inhibit bit in the Re-
ceiver Control Register is set, all characters in the