ADAU1373BCBZ-RL AD [Analog Devices], ADAU1373BCBZ-RL Datasheet - Page 150

• Manufacturer Part Number: ADAU1373BCBZ-RL
• Description: Low Power Codec with Speaker and Headphone Amplifier
• Manufacturer: AD [Analog Devices]

ADAU1373
CLK2_SOURCE_DIV REGISTER
Address: 0x42, Reset: 0x00, Name: CLK2_SOURCE_DIV
Clock 2 Divide and Core Clock Enable Control
Table 95. Bit Descriptions for CLK2_SOURCE_DIV
Bits
7
6
[5:3]
[2:0]
Bit Name
CLK2EN
CLK2S_SEL
CLK2SDIV
MCLK2DIV
Settings
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
0
1
0
1
Description
Clock 2 Enable. Core clock enable or disable control.
Clock 2 disable (default)
Clock 2 enable
PLLB Bypass Signal. Clock source selection. Clock source can be set to
either PLLB output or external input.
Use PLLB clock as Source Clock 2 (default)
Use external clock as Source Clock 2
Source Clock 2 Divider. Source Clock 2 divider settings, 0 through 7 in
eight steps.
Source Clock Divider K = 0
Source Clock Divider K = 1
Source Clock Divider K = 2
Source Clock Divider K = 3
Source Clock Divider K = 4
Source Clock Divider K = 5
Source Clock Divider K = 6
Source Clock Divider K = 7
Master Clock 2 Divider. Master Clock 2 divider settings, 0 through 7 in
eight steps.
Divider J = 0
Divider J = 1
Divider J = 2
Divider J = 3
Divider J = 4
Divider J = 5
Divider J = 6
Divider J = 7
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Reset
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW