ADAU1373BCBZ-RL AD [Analog Devices], ADAU1373BCBZ-RL Datasheet - Page 45

• Manufacturer Part Number: ADAU1373BCBZ-RL
• Description: Low Power Codec with Speaker and Headphone Amplifier
• Manufacturer: AD [Analog Devices]

In addition, the amplifier provides edge rate control. The edge rate
control can be used to set the switching output slew rate for precise
EMI control. The edge rate can be used to reduce EMI in the
30 MHz to 100 MHz band. The slower edge rate reduces EMI
but also compromises audio performance. The higher edge rate
improves audio performance, but there is more energy in the
30 MHz to 100 MHz band than at the lower edge rate. The EDGE
bits (Bits[1:0]) in Register 0x1F can be used for edge rate control.
If only the DAC output is used during playback through the
speaker, a mode is available that allows the DAC output to be
sent directly and internally to the speaker simplifier block input
instead of passing it through the mixer stage, which improves
the signal-to-noise ratio at the speaker output by 6 dB. However,
in this mode, the speaker mixer block is disabled, and only the
DAC output can be routed to the speaker amplifier. The DIRCD
bit (Bit 6) in Register 0x1F is used to enable this feature.
ANALOG-TO-DIGITAL CONVERTER (ADC)
The ADAU1373 consists of a stereo sigma-delta (Σ-Δ) ADC.
The ADC uses a 128 × f
signal to the ADC is provided via the ADC mixer. Any or all of
the four inputs can be selected to be sent to the ADC using the
ADCLMIXx bits (Bits[4:0]) in Register 0x12 for the left channel
and the ADCRMIXx bits (Bits[4:0]) in Register 0x13 for the right
channel. The ADC output can be made available on the digital
audio ports or sent to the on-chip DAC for analog output.
ADC Full-Scale Level
The full-scale input to the ADCs (0 dBFS) depends on AVDD.
At AVDD = 3.3 V, the full-scale input level is 0.55 V rms single-
ended or 1 V rms differential. The full-scale input level scales
linearly with the level of AVDD. For single-ended and pseudo-
differential signals, the full-scale value corresponds to the signal
level at the pins, which is 0 dBFS. Signal levels above the full-scale
value cause the ADCs to clip.
Figure 91. Amplifier Connection Diagram, Mono Mode
+12dB/18dB
LEFT AND
ADAU1373
RIGHT
S
clock and 24-bit resolution. The input
PLL TOP LEVEL
LRCLKA
LRCLKB
LRCLKC
BCLKA
BCLKB
BCLKC
MCLK1
MCLK2
GPIO1
GPIO2
GPIO3
GPIO4
SPKLP
SPKLN
SPKRP
SPKRN
CLOCK > 8MHz
CLOCK < 8MHz
Figure 92. PLL Top Level Block Diagram
÷ Nd
DPLL
Rev. 0 | Page 45 of 296
× Md
Digital ADC Volume Control
The ADC output level can be controlled before DSP processing
in Register 0x72 (ADC left channel recording volume control)
and Register 0x73 (ADC right channel recording volume control).
Peak Detect
The ADC has a peak detection feature that can be enabled or
disabled using the PDETECT bit (Bit 0) in Register 0x3C.
ADC RESET
The ADC can be reset by writing Bits[2:1] = 11 in Register 0x3C.
By default, ADC reset is disabled.
ADC STATUS
The ADC status bits are available for reading via the NOCLKADC
bit (Bit 0) in Register 0x37.
DIGITAL-TO-ANALOG CONVERTER (DAC)
The ADAU1373 consists of two stereo Σ-Δ DACs (DAC1 and
DAC2). Each DAC uses a 128 × f
The DACs receive input from either the DSP or the ADC.
DAC output can be routed to the line output, headphone output,
earpiece output, or speaker output.
DAC Full-Scale Level
The full-scale output for the DAC, with 0 dBFS input, depends on
AVDD. At AVDD = 3.3 V, the full-scale output level is 0.55 V rms
single-ended or 1 V rms differential. The full-scale input level
scales linearly with the level of AVDD.
Digital DAC Volume Control
The DAC output level can be attenuated using Register 0x6E
(DAC1 left channel playback volume control), Register 0x6F
(DAC1 right channel playback volume control), Register 0x70
(DAC2 left channel playback volume control), and Register 0x71
(DAC2 right channel playback volume control).
DAC Status
The DAC status bits are available for reading at Bits[6:5] in
Register 0x37.
CLOCK GENERATION AND DISTRIBUTION
The ADAU1373 requires an external clock for operation. Flexible
clocking control enables the use of many different input clock
rates. The on-chip PLL can be used to dejitter the external clock.
Two identical PLL blocks, PLLA and PLLB, are provided and
can be bypassed if not required. Figure 92 shows the top level
block diagram for PLL.
÷ X
APLL
×(R + N/M)
44.1kHz × 1024/
48kHz × 1024
S
clock and 24-bit resolution.
ADAU1373