ADAU1373BCBZ-RL AD [Analog Devices], ADAU1373BCBZ-RL Datasheet - Page 50

• Manufacturer Part Number: ADAU1373BCBZ-RL
• Description: Low Power Codec with Speaker and Headphone Amplifier
• Manufacturer: AD [Analog Devices]

ADAU1373
PLL Mode
If using the PLL, set the dividers so that f
of 45.158 MHz (1024 kHz × 44.1 kHz) to 49.152 MHz (1024 kHz ×
48 kHz).
Example 1—Using a PLL Sample Rate of 48 kHz
For a 48 kHz sample rate (f
within the range of 45 MHz to 50 MHz.
where D = (J + 1) × (K + 1).
For D = 3, f
and for D = 5, f
is within the PLL range of 45 MHz to 50 MHz.
To determine the divider values, there are two options, as follows:
•
•
Example 2—Using a PLL Sample Rate of 44.1 kHz
For a 44.1 kHz sample rate (f
within the range of 45 MHz to 50 MHz.
where D = (J + 1) × (K + 1).
For D = 3, f
for D = 5, f
within the PLL range of 45 MHz to 50 MHz.
To determine the divider values, there are two options, as follows:
•
•
Example 3—Using a PLL Sample Rate of 32 kHz
For a 32 kHz sample rate (f
within the range of 45 MHz to 50 MHz.
where D = (J + 1) × (K + 1).
f
f
By setting J = K = 1, then D = 4 because D = (J + 1) × (K + 1).
By setting J = 0, K = 3 also results in D = (J + 1) × (K + 1) = 4.
f
By setting J = K = 1, then D = 4 because X = (J + 1) × (K + 1).
By setting J = 0, K = 3 also results in D = (J + 1) × (K + 1) = 4.
f
PLL
PLL
PLL
PLL
= 256 × f
= 256 × D × 48,000
= 256 × D × 44,100
= 256 × D × 32,000
PLL
PLL
PLL
= 56.448 MHz. Setting D = 4 ensures that f
= 36.864 MHz; for D = 4, f
= 33.868 MHz; for D = 4, f
PLL
S
= 61.44 MHz. Setting D = 4 ensures that f
× (J + 1) × (K + 1)
S
S
), select the J and K such that f
), select the J and K such that f
S
), select the J and K such that f
PLL
PLL
PLL
is within the range
= 49.152 MHz;
= 45.158 MHz; and
PLL
PLL
PLL
PLL
is
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PLL
is
is
is
For D =5, f
for D = 7, f
within the PLL range of 45 MHz to 50 MHz.
To determine the divider values, there are two options, as follows:
•
•
Step 3—Calculate APLL multiplier/dividers (X, R, N, M)
If using the analog PLL only, then f
Next, using the f
N, and M values.
For integer mode, use the following:
N and M are ignored.
For fractional mode, use the following:
Select the values of R and X for integer mode or R, X, N, and M
for fractional mode.
If the available clock in the system (f
PLL output frequency (f
X, R, N, and M for fractional mode or X and R for integer mode
can be calculated using the following equation:
Wide selections are possible; refer to Table 11, Table 12, and
Table 13 for popular choices.
Step 4—Master Clock Output
The internal core clock, f
GPIO1/GPIO2/GPIO3/GPIO4 pins by setting Register 0xE3
or Register 0xE4. The master clock output frequency can
be set using the 5-bit divider (Register 0x41 for PLLA and
Register 0x43 for PLLB). Table 17 lists the registers that are
used to set the PLL, and Table 18 provides descriptions of the
48 bits that are used for PLL control.
Setting J = 1 and K = 2 can result in D = 6.
Setting J = 0 and K = 5 also results in D = 6.
f
f
(R/X) = f
(R + N/M)/X = f
PLL
PLL
= (R/X) × f
= f
PLL
PLL
IN
× (R + (N/M))/X
IN
= 57.344 MHz. Setting D = 6 ensures that f
= 40.96 MHz; for D = 6, f
/f
PLL
PLL
calculated in Step 2, calculate the PLL X, R,
IN
(integer mode)
IN
/f
PLL
PLL
CORE
) from Step 2, the values required for
(fractional mode)
, can be made available at the
IN
IN
≥ 8 MHz.
) is known, and using the
PLL
= 49.152 MHz; and
PLL
is