ADAU1373BCBZ-RL AD [Analog Devices], ADAU1373BCBZ-RL Datasheet - Page 51

• Manufacturer Part Number: ADAU1373BCBZ-RL
• Description: Low Power Codec with Speaker and Headphone Amplifier
• Manufacturer: AD [Analog Devices]

Table 17. PLL Control Register Summary
Reg Name
0x28 DPLLA_CTRL
0x29 PLLA_CTRL1
0x2A PLLA_CTRL2
0x2B PLLA_CTRL3
0x2C PLLA_CTRL4
0x2D PLLA_CTRL5 RESERVED
0x2E PLLA_CTRL6
0x2F DPLLB_CTRL
0x30 PLLB_CTRL1
0x31 PLLB_CTRL2
0x32 PLLB_CTRL3
0x33 PLLB_CTRL4
0x34 PLLB_CTRL5 RESERVED
0x35 PLLB_CTRL6
0x40 CLK1_
0x41 CLK1_
0x42 CLK2_
0x43 CLK2_
Table 18. PLLA/PLLB Control Register Settings (PLLA: Register 0x28 to Register 0x2E; PLLB: Register 0x2F to Register 0x35)
Bits
[47:32]
[31:16]
[15]
[14:11]
[10:9]
8
[7:4]
SOURCE_DIV
OUTPUT_DIV
SOURCE_DIV
OUTPUT_DIV
Bit Name
PLLx_M_HI[7:0],
PLLx_M_LO[7:0]
PLLx_N_HI[7:0],
PLLx_N_LO[7:0]
Reserved
PLLx_R[3:0]
PLLx_X[1:0]
PLLx_TYPE
Reserved
Bit 7
COREN
CLK2EN
RESERVED
RESERVED
CLK1S_SEL
CLK2S_SEL
Bit 6
Settings
DPLLA_REF_SEL
DPLLB_REF_SEL
RESERVED
RESERVED
CLK1OEN
CLK2OEN
Bit 5
0010
0011
0100
0101
0110
0111
1000
00
01
10
11
0
1
PLLA_R
PLLB_R
Description
Denominator of the fractional APLL: a 16-bit binary number. The PLLA/PLLB Control M
value can be set using Register 0x29 and Register 0x2A for PLLA and Register 0x30 and
Register 0x31 for PLLB. The M integer is 16 bits wide. The upper eight bits are stored in
Register 0x29 and Register 0x30, and the lower eight bits are stored in Register 0x2A and
Register 0x31. The default value is 0x00FD: M = 253.
Numerator of the fractional APLL: a 16-bit binary number. The N value can be set using
Register 0x2B and Register 0x2C for PLLA and Register 0x32 and Register 0x33 for PLLB.
The upper eight bits are stored in Register 0x2B and Register 0x32, and the lower eight
bits are stored in Register 0x2C and Register 0x33. The default value is 0: N = 0.
Reserved.
Integer part of APLL: four bits. Only values of 2 to 8 are valid. The four bits are stored in
Register 0x2D for PLLA (Bits[6:3]) and Register 0x34 for PLLB (Bits[6:3]).
R = 2 (default).
R = 3.
R = 4.
R = 5.
R = 6.
R = 7.
R = 8.
APLL input clock divider. The two bits are stored in Register 0x2D for PLLA (Bits[2:1]) and
Register 0x34 for PLLB (Bits[2:1]).
X = 1 (default).
X = 2.
X = 3.
X = 4.
APLL operation mode. This bit is stored in Register 0x2D for PLLA (Bit 0) and Register 0x34
for PLLB (Bit 0).
Integer mode (default).
Fractional mode.
Reserved.
Bit 4
CLK1SDIV
CLK2SDIV
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Bit 3
DPLLA_LOCKED
DPLLB_LOCKED
PLLA_M_LO
PLLA_N_LO
PLLB_M_LO
PLLA_M_HI
PLLB_N_LO
PLLA_N_HI
PLLB_M_HI
PLLB_N_HI
PLLA_LOCKED
PLLB_LOCKED
Bit 2
DPLLA_NDIV
DPLLB_NDIV
CLK1ODIV
CLK2ODIV
PLLA_X
PLLB_X
DPLLA_BYPASS
DPLLB_BYPASS
MCLK1DIV
MCLK2DIV
Bit 1
PLLA_TYPE
PLLA_EN
PLLB_TYPE
PLLB_EN
Bit 0
ADAU1373
Reset RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x10 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x02 RW
0x00 MMRW
0x00 RW
0x00 MMRW
0x00 RW