PIC18F23K20-E/MLQTP MICROCHIP [Microchip Technology], PIC18F23K20-E/MLQTP Datasheet - Page 162

• Manufacturer Part Number: PIC18F23K20-E/MLQTP
• Description: 28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2XK20/4XK20
15.4.1
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 15-1.
EQUATION 15-1:
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCPx pin is set. (Exception: If the PWM duty
• The PWM duty cycle is latched from CCPR
DS41303B-page 160
cycle = 0%, the pin will not be set.)
CCPR
Note:
Note: T
PWM Period
x
H.
PWM PERIOD
The Timer2 postscaler (see Section 13.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency.
OSC
= 1/F
=
(TMR2 Prescale Value)
[
PWM PERIOD
(
OSC
PR2
.
)
+
1
] 4 T
•
•
OSC
Advance Information
•
x
L into
15.4.2
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPR
DCxB<1:0> bits of the CCPxCON register. The
CCPR
bits of the CCPxCON register contain the two LSbs.
CCPR
register can be written to at any time. The duty cycle
value is not latched into CCPR
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPR
register is read-only.
Equation 15-2 is used to calculate the PWM pulse
width.
Equation 15-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 15-2:
EQUATION 15-3:
The CCPR
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (F
the prescaler, to create the 10-bit time base. The system
clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPR
2-bit latch, then the CCPx pin is cleared (see
Figure 15-3).
Duty Cycle Ratio
x
x
Pulse Width
L contains the eight MSbs and the DCxB<1:0>
L and DCxB<1:0> bits of the CCPxCON
x
PWM DUTY CYCLE
H register and a 2-bit internal latch are
=
T
OSC
(
=
PULSE WIDTH
DUTY CYCLE RATIO
CCPRxL:DCxB<1:0>
© 2007 Microchip Technology Inc.
(
---------------------------------------------------------- -
CCPRxL:DCxB<1:0>
•
(TMR2 Prescale Value)
4 PR2
x
H until after the period
(
x
+
OSC
L register and
1
)
), or 2 bits of
)
•
)
x
H and
x
H