PIC18F23K20-E/MLQTP MICROCHIP [Microchip Technology], PIC18F23K20-E/MLQTP Datasheet - Page 255

• Manufacturer Part Number: PIC18F23K20-E/MLQTP
• Description: 28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

18.4.2.3
The operation of the Synchronous Master and Slave
modes is identical (Section 18.4.1.6 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don't care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
© 2007 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCTL
SPBRGH
SPBRG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Note 1:
never Idle
Name
Reserved in 28-pin devices; always maintain these bits clear.
EUSART Synchronous Slave
Reception
EUSART Receive Register
EUSART Baud Rate Generator Register, High Byte
EUSART Baud Rate Generator Register, Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
PSPIE
PSPIP
PSPIF
CSRC
SPEN
Bit 7
(1)
(1)
(1)
RCIDL
ADIE
ADIP
Bit 6
ADIF
RX9
TX9
DTRXP
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
Advance Information
CKTXP
INT0IE
CREN
SYNC
Bit 4
TXIF
TXIE
TXIP
ADDEN
SENDB
BRG16
18.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
SSPIF
SSPIE
SSPIP
PIC18F2XK20/4XK20
RBIE
Bit 3
Set the SYNC and SPEN bits and clear the
CSRC bit. Set the TRIS bits corresponding to
the RX/DT and TX/CK I/O pins.
If using interrupts, ensure that the GIE and PEIE
bits of the INTCON register are set and set the
RCIE bit.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
Synchronous Slave Reception
Set-up:
—
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
WUE
Bit 1
TMR1IE
TMR1IP
TMR1IF
ABDEN
RX9D
TX9D
RBIF
DS41303B-page 253
Bit 0
on page
Values
Reset
57
60
60
60
59
59
59
59
59
59