PIC18F23K20-E/MLQTP MICROCHIP [Microchip Technology], PIC18F23K20-E/MLQTP Datasheet - Page 49

• Manufacturer Part Number: PIC18F23K20-E/MLQTP
• Description: 28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

3.5.4
Certain exits from power-managed modes do not
invoke the OST at all. There are two cases:
• PRI_IDLE mode, where the primary clock source
• the primary clock source is not any of the LP, XT,
TABLE 3-3:
© 2007 Microchip Technology Inc.
Note 1:
is not stopped and
HS or HSPLL modes.
T1OSC or LFINTOSC
Primary Device Clock
2:
3:
4:
(PRI_IDLE mode)
before Wake-up
Clock Source
HFINTOSC
(Sleep mode)
T
with any other required delays (see Section 3.4 “Idle Modes”). On Reset, HFINTOSC defaults to 1 MHz.
Includes both the HFINTOSC 16 MHz source and postscaler derived frequencies.
T
Execution continues during the HFINTOSC stabilization period, T
EXIT WITHOUT AN OSCILLATOR
START-UP DELAY
CSD
OST
None
(parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently
is the Oscillator Start-up Timer (parameter 32). t
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
(2)
(1)
after Wake-up
Clock Source
HFINTOSC
HFINTOSC
HFINTOSC
HFINTOSC
Advance Information
LP, XT, HS
LP, XT, HS
LP, XT, HS
LP, XT, HS
EC, RC
EC, RC
EC, RC
EC, RC
HSPLL
HSPLL
HSPLL
HSPLL
(2)
(1)
(1)
(1)
In these instances, the primary clock source either
does not require an oscillator start-up delay since it is
already running (PRI_IDLE), or normally does not
require an oscillator start-up delay (RC, EC, INTOSC,
and INTOSCIO modes). However, a fixed delay of
interval T
when leaving Sleep and Idle modes to allow the CPU
to prepare for execution. Instruction execution resumes
on the first clock cycle following this delay.
PIC18F2XK20/4XK20
PLL
is the PLL Lock-out Timer (parameter F12).
CSD
T
T
T
OST
OST
OST
Exit Delay
T
T
T
T
T
T
T
T
T
IOBST
IOBST
IOBST
following the wake event is still required
None
CSD (1)
OST
CSD
OST
CSD
OST
CSD
+ t
+ t
+ t
(3)
PLL
(1)
(4)
PLL
(1)
(3)
PLL
(1)
(4)
(4)
(parameter 39).
(3)
(3)
(3)
Clock Ready Status
Bit (OSCCON)
DS41303B-page 47
OSTS
OSTS
OSTS
OSTS
IOFS
IOFS
IOFS
IOFS