PIC18F23K20-E/MLQTP MICROCHIP [Microchip Technology], PIC18F23K20-E/MLQTP Datasheet - Page 80

• Manufacturer Part Number: PIC18F23K20-E/MLQTP
• Description: 28/40/44-Pin Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2XK20/4XK20
TABLE 5-2:
DS41303B-page 78
TMR0H
TMR0L
T0CON
OSCCON
HLVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
PSTRCON
BAUDCTL
PWM1CON
ECCP1AS
CVRCON
CVRCON2
TMR3H
TMR3L
T3CON
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, — = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise it is disabled and reads as ‘0’. See
Section 4.4 “Brown-out Reset (BOR)”.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise it is disabled and reads as ‘0’. See Section 2.6.2 “PLL in
HFINTOSC Modes”.
The RE3 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0). Otherwise, RE3 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
All bits of the ANSELH register initialize to ‘0’ if the PBADEN bit of CONFIG3H is ‘0’.
Timer0 Register, High Byte
Timer0 Register, Low Byte
Timer1 Register, High Byte
Timer1 Register, Low Bytes
Timer2 Register
Timer2 Period Register
SSP Receive Buffer/Transmit Register
SSP Address Register in I
A/D Result Register, High Byte
A/D Result Register, Low Byte
Capture/Compare/PWM Register 1, High Byte
Capture/Compare/PWM Register 1, Low Byte
Capture/Compare/PWM Register 2, High Byte
Capture/Compare/PWM Register 2, Low Byte
Timer3 Register, High Byte
Timer3 Register, Low Byte
VDIRMAG
ECCPASE
TMR0ON
ABDOVF
CVREN
PRSEN
FVREN
IDLEN
WCOL
GCEN
ADFM
P1M1
RD16
RD16
IPEN
Bit 7
SMP
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F2XK20/4XK20) (CONTINUED)
SBOREN
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
ACKSTAT
ECCPAS2
T3CCP2
CVROE
SSPOV
T08BIT
T1RUN
FVRST
IRCF2
RCIDL
P1M0
PDC6
Bit 6
CKE
—
—
—
—
—
—
—
(1)
2
C™ Slave Mode. SSP Baud Rate Reload Register in I
ECCPAS1
T1CKPS1
T3CKPS1
SSPEN
ACKDT
VCFG1
ACQT2
DTRXP
DC1B1
DC2B1
IRCF1
IRVST
CVRR
CHS3
PDC5
T0CS
Bit 5
D/A
—
—
—
—
Advance Information
STRSYNC
ECCPAS0
T1CKPS0
T3CKPS0
HLVDEN
ACKEN
CVRSS
VCFG0
ACQT1
CKTXP
DC1B0
DC2B0
IRCF0
CHS2
PDC4
T0SE
Bit 4
CKP
—
RI
—
P
T1OSCEN
CCP1M3
CCP2M3
PSSAC1
HLVDL3
T3CCP1
SSPM3
ACQT0
BRG16
RCEN
OSTS
CHS1
STRD
PDC3
CVR3
Bit 3
PSA
TO
—
—
—
S
TMR2ON
CCP1M2
CCP2M2
T1SYNC
PSSAC0
T3SYNC
HLVDL2
SSPM2
ADCS2
T0PS2
CHS0
STRC
PDC2
CVR2
IOFS
Bit 2
R/W
PEN
PD
—
—
—
—
2
C Master Mode.
GO/DONE
T2CKPS1
TMR1CS
TMR3CS
CCP1M1
CCP2M1
PSSBD1
HLVDL1
SSPM1
ADCS1
T0PS1
RSEN
PDC1
SCS1
STRB
CVR1
Bit 1
WUE
POR
UA
—
—
—
© 2007 Microchip Technology Inc.
T2CKPS0
SWDTEN
TMR1ON
TMR3ON
CCP1M0
CCP2M0
PSSBD0
HLVDL0
SSPM0
ADCS0
ABDEN
T0PS0
ADON
STRA
PDC0
CVR0
SCS0
Bit 0
BOR
SEN
BF
—
—
0000 0000
xxxx xxxx
1111 1111
0011 qq00
0-00 0101
0q-1 11q0
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
--00 ----
0-00 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
---0 0001
0100 0-00
0000 0000
0000 0000
0000 0000
00-- ----
xxxx xxxx
xxxx xxxx
0000 0000
POR, BOR
--- ---0
Value on
on page:
58, 193,
58, 187,
58, 187,
Details
58, 139
58, 139
58, 137
58, 283
58, 299
58, 146
58, 146
58, 141
58, 148
58, 148
58, 147
58, 194
58, 197
59, 267
59, 267
59, 261
59, 262
59, 263
59, 154
59, 154
59, 165
59, 154
59, 154
59, 153
59, 179
59, 238
59, 178
59, 175
59, 281
59, 282
59, 151
59, 151
59, 149
49, 56,
27, 58
114
194
196
196